HAL  v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
Deprecated List
Member hal::BooleanFunction::to_z3 (z3::context &context, const std::map< std::string, z3::expr > &var2expr={}) const
DEPRECATED
Translates the Boolean function into the z3 expression representation.
Member hal::GraphicsScene::snapToGrid (const QPointF &pos) Q_DECL_DEPRECATED
Please use GraphGraphicsView::closestLayouterPos instead.
Member hal::netlist_utils::copy_netlist (const Netlist *nl)
Get a deep copy of an entire netlist including all of its gates, nets, modules, and groupings.
Member hal::netlist_utils::get_next_gates (const Gate *gate, bool get_successors, int depth=0, const std::function< bool(const Gate *)> &filter=nullptr)
Find predecessors or successors of a gate. If depth is set to 1 only direct predecessors/successors will be returned. Higher number of depth causes as many steps of recursive calls. If depth is set to 0 there is no limitation and the loop continues until no more predecessors/succesors are found. If a filter function is given only gates matching the filter will be added to the result vector. The result will not include the provided gate itself.
Member hal::netlist_utils::get_next_gates (const Net *net, bool get_successors, int depth=0, const std::function< bool(const Gate *)> &filter=nullptr)
Find predecessors or successors of a net. If depth is set to 1 only direct predecessors/successors will be returned. Higher number of depth causes as many steps of recursive calls. If depth is set to 0 there is no limitation and the loop continues until no more predecessors/succesors are found. If a filter function is given, the recursion stops whenever the filter function evaluates to false. Only gates matching the filter will be added to the result vector.
Member hal::netlist_utils::get_next_sequential_gates (const Gate *gate, bool get_successors, std::unordered_map< u32, std::vector< Gate * >> &cache)
Find all sequential predecessors or successors of a gate. Traverses combinational logic of all input or output nets until sequential gates are found. The result may include the provided gate itself. The use of the this cached version is recommended in case of extensive usage to improve performance. The cache will be filled by this function and should initially be provided empty. Different caches for different values of get_successors shall be used.
Member hal::netlist_utils::get_next_sequential_gates (const Gate *gate, bool get_successors)
Find all sequential predecessors or successors of a gate. Traverses combinational logic of all input or output nets until sequential gates are found. The result may include the provided gate itself.
Member hal::netlist_utils::get_next_sequential_gates (const Net *net, bool get_successors, std::unordered_map< u32, std::vector< Gate * >> &cache)
Find all sequential predecessors or successors of a net. Traverses combinational logic of all input or output nets until sequential gates are found. The use of the cache is recommended in case of extensive usage of this function. The cache will be filled by this function and should initially be provided empty. Different caches for different values of get_successors shall be used.
Member hal::netlist_utils::get_next_sequential_gates (const Net *net, bool get_successors)
Find all sequential predecessors or successors of a net. Traverses combinational logic of all input or output nets until sequential gates are found.
Member hal::netlist_utils::get_partial_netlist (const Netlist *nl, const std::vector< const Gate * > &subgraph_gates)
Get a deep copy of an entire partial netlist including all of its gates, nets, excluding modules and groupings.
Member hal::netlist_utils::get_subgraph_function (const Net *net, const std::vector< const Gate * > &subgraph_gates, std::map< std::pair< u32, const GatePin * >, BooleanFunction > &cache)
Get the combined Boolean function of a subgraph of combinational gates starting at the source of the given net. The variables of the resulting Boolean function are made up of the IDs of the nets that influence the output ('net_[ID]'). Utilizes a cache for speedup on consecutive calls.
Member hal::netlist_utils::get_subgraph_function (const Net *net, const std::vector< const Gate * > &subgraph_gates)
Get the combined Boolean function of a subgraph of combinational gates starting at the source of the given net. The variables of the resulting Boolean function are made up of the IDs of the nets that influence the output ('net_[ID]').
Member hal::netlist_utils::remove_buffers (Netlist *netlist, bool analyze_inputs=false)
Remove all buffer gates from the netlist and connect their fan-in to their fan-out nets. If enabled, analyzes every gate's inputs and removes fixed '0' or '1' inputs from the Boolean function.
Member hal::netlist_utils::remove_unused_lut_endpoints (Netlist *netlist)
Remove all LUT fan-in endpoints that are not present within the Boolean function of the output of a gate.
Member hal::netlist_utils::replace_gate (Gate *gate, GateType *target_type, std::map< GatePin *, GatePin * > pin_map)
Replace the given gate with a gate of the specified gate type. A map from old to new pins must be provided in order to correctly connect the gates inputs and outputs. A pin can be omitted if no connection at that pin is desired.
Member hal::NetlistSimulator::load_initial_values (BooleanFunction::Value value)
DEPRECATED
Load the specified initial value into the current state of all sequential elements.
Member hal::NetlistSimulator::load_initial_values_from_netlist ()
DEPRECATED
Load the initial value specified within the netlist file into the current state of all sequential elements. This is especially relevant for FPGA netlists, since these may provide initial values to load on startup.