|
HAL
v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
|
#include </home/runner/work/hal/hal/plugins/verilog_parser/include/verilog_parser/verilog_parser.h>


Public Member Functions | |
| VerilogParser ()=default | |
| ~VerilogParser ()=default | |
| Result< std::monostate > | parse (const std::filesystem::path &file_path) override |
| Result< std::unique_ptr< Netlist > > | instantiate (const GateLibrary *gate_library) override |
Public Member Functions inherited from hal::NetlistParser | |
| NetlistParser ()=default | |
| virtual | ~NetlistParser ()=default |
| Result< std::unique_ptr< Netlist > > | parse_and_instantiate (const std::filesystem::path &file_path, const GateLibrary *gate_library) |
A netlist parser for gate-level Verilog.
Definition at line 50 of file verilog_parser.h.
|
default |
|
default |
|
overridevirtual |
Instantiate the parsed Verilog netlist using the specified gate library.
| [in] | gate_library | - The gate library. |
Implements hal::NetlistParser.
Definition at line 238 of file verilog_parser.cpp.
References hal::Netlist::create_net(), hal::netlist_factory::create_netlist(), hal::Netlist::delete_net(), ERR, ERR_APPEND, hal::GateLibrary::get_gate_types(), hal::GateLibrary::get_gnd_gate_types(), hal::GateLibrary::get_name(), hal::Net::get_name(), hal::Netlist::get_nets(), hal::GateLibrary::get_vcc_gate_types(), hal::Netlist::load_gate_locations_from_data(), hal::ShortestPath::module(), name, net, and OK.
|
overridevirtual |
Parse a Verilog netlist into an internal intermediate format.
| [in] | file_path | - Path to the Verilog netlist file. |
true on success, false otherwise. Implements hal::NetlistParser.
Definition at line 22 of file verilog_parser.cpp.
References ERR, ERR_APPEND, and OK.