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HAL
v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
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#include </home/runner/work/hal/hal/plugins/verilog_writer/include/verilog_writer/verilog_writer.h>


Public Member Functions | |
| VerilogWriter ()=default | |
| ~VerilogWriter ()=default | |
| Result< std::monostate > | write (Netlist *netlist, const std::filesystem::path &file_path) override |
Public Member Functions inherited from hal::NetlistWriter | |
| NetlistWriter ()=default | |
| virtual | ~NetlistWriter ()=default |
A netlist writer that serializes a netlist into gate-level Verilog.
Definition at line 49 of file verilog_writer.h.
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default |
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default |
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overridevirtual |
Write the netlist to a Verilog file at the provided location.
| [in] | netlist | - The netlist. |
| [in] | file_path | - The output path. |
true on success, false otherwise. Implements hal::NetlistWriter.
Definition at line 15 of file verilog_writer.cpp.
References ERR, ERR_APPEND, hal::Netlist::get_modules(), and OK.