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HAL
v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
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Functions | |
| NetlistAbstraction | run (const dataflow::Configuration &config, std::shared_ptr< dataflow::Grouping > &initial_grouping) |
| void | identify_register_stages (NetlistAbstraction &netlist_abstr) |
The pre-processing phase of dataflow analysis, which builds the netlist abstraction that the later phases operate on.
| void hal::dataflow::pre_processing::identify_register_stages | ( | NetlistAbstraction & | netlist_abstr | ) |
Definition at line 24 of file register_stage_identification.cpp.
References hal::dataflow::ProgressPrinter::clear(), hal::dataflow::NetlistAbstraction::gate_to_predecessors, hal::dataflow::NetlistAbstraction::gate_to_register_stages, hal::dataflow::NetlistAbstraction::gate_to_successors, log_info, measure_block_time, name, hal::dataflow::ProgressPrinter::print_progress_to_stderr(), and hal::dataflow::NetlistAbstraction::target_gates.
Referenced by run().
| NetlistAbstraction hal::dataflow::pre_processing::run | ( | const dataflow::Configuration & | config, |
| std::shared_ptr< dataflow::Grouping > & | initial_grouping | ||
| ) |
Definition at line 323 of file pre_processing.cpp.
References hal::dataflow::Configuration::enable_stages, identify_register_stages(), log_info, measure_block_time, and hal::dataflow::Configuration::netlist.
Referenced by hal::dataflow::analyze().