HAL  v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
hal::module_identification::xilinx_unisim Namespace Reference

Functions

std::vector< std::pair< std::unique_ptr< BaseCandidate >, std::vector< std::unique_ptr< StructuralCandidate > > > > generate_structural_candidates (const Netlist *nl)
 Generate structural candidates for a given netlist. More...
 

Detailed Description

The gate type properties of the Xilinx UNISIM architecture that module identification needs, e.g., which types are carry chains.

Function Documentation

◆ generate_structural_candidates()

std::vector< std::pair< std::unique_ptr< BaseCandidate >, std::vector< std::unique_ptr< StructuralCandidate > > > > hal::module_identification::xilinx_unisim::generate_structural_candidates ( const Netlist nl)

Generate structural candidates for a given netlist.

This function generates structural candidates by analyzing the netlist of a Xilinx Unisim library. The structural candidates are generated based on the identification carry chains used in Xilinx FPGAs to implement arithemetic operations. It returns a vector of pairs, where each pair contains a unique pointer to a BaseCandidate and a vector of unique pointers to StructuralCandidate objects.

Parameters
[in]nl- The netlist to operate on.
Returns
A vector of pairs, each containing a BaseCandidate and a vector of corresponding StructuralCandidate objects.

Definition at line 675 of file xilinx_unisim.cpp.

References log_info.

Referenced by hal::module_identification::generate_structural_candidates().