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HAL
v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
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#include "solve_fsm/solve_fsm.h"#include "hal_core/netlist/boolean_function/solver.h"#include "hal_core/netlist/decorators/boolean_function_decorator.h"#include "hal_core/netlist/decorators/boolean_function_net_decorator.h"#include "hal_core/netlist/decorators/subgraph_netlist_decorator.h"#include "hal_core/netlist/gate.h"#include "hal_core/netlist/gate_library/gate_type.h"#include "hal_core/netlist/gate_library/gate_type_component/ff_component.h"#include "hal_core/netlist/gate_library/gate_type_component/state_component.h"#include "hal_core/plugin_system/plugin_manager.h"#include "hal_core/plugin_system/gui_extension_interface.h"#include "hal_core/netlist/net.h"#include <bitset>#include <fstream>#include <deque>
Go to the source code of this file.
Namespaces | |
| hal | |
| hal::solve_fsm | |
Functions | |
| Result< std::map< u64, std::map< u64, BooleanFunction > > > | hal::solve_fsm::solve_fsm_brute_force (Netlist *nl, const std::vector< Gate * > &state_reg, const std::vector< Gate * > &transition_logic, const std::filesystem::path &graph_path="") |
| Result< std::map< u64, std::map< u64, BooleanFunction > > > | hal::solve_fsm::solve_fsm (Netlist *nl, const std::vector< Gate * > &state_reg, const std::vector< Gate * > &transition_logic, const std::map< Gate *, bool > &initial_state={}, const std::filesystem::path &graph_path="", const u32 timeout=600000) |
| Result< std::string > | hal::solve_fsm::generate_dot_graph (const std::vector< Gate * > &state_reg, const std::map< u64, std::map< u64, BooleanFunction >> &transitions, const std::filesystem::path &graph_path="", const u32 max_condition_length=128, const u32 base=10) |