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HAL
v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
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Go to the source code of this file.
Namespaces | |
| hal | |
| hal::z3_utils | |
Functions | |
| Result< z3::expr > | hal::z3_utils::get_subgraph_z3_function (const std::vector< Gate * > &subgraph_gates, const Net *subgraph_output, z3::context &ctx) |
| Get the z3 expression representation of a combined Boolean function of a subgraph of combinational gates starting at the source of the provided subgraph output net. More... | |
| Result< std::vector< z3::expr > > | hal::z3_utils::get_subgraph_z3_functions (const std::vector< Gate * > &subgraph_gates, const std::vector< Net * > &subgraph_outputs, z3::context &ctx) |
| Get the z3 expression representations of combined Boolean functions of a subgraph of combinational gates starting at the sources of the provided subgraph output nets. More... | |