36 for (
const auto* mod : structures)
38 for (
const auto* pin_group : mod->get_pin_groups())
40 std::vector<Net*> nets;
41 for (
const auto* pin : pin_group->get_pins())
43 nets.push_back(pin->get_net());
59 for (
const auto& [_, pin_groups] : structures)
61 for (
const auto* pin_group : pin_groups)
63 std::vector<Net*> nets;
64 for (
const auto* pin : pin_group->get_pins())
66 nets.push_back(pin->get_net());
82 for (
const auto* gate : structures)
84 for (
const auto* pin_group : gate->get_type()->get_pin_groups())
86 std::vector<Net*> nets;
87 for (
const auto* pin : pin_group->get_pins())
91 nets.push_back(gate->get_fan_in_net(pin));
95 nets.push_back(gate->get_fan_out_net(pin));
112 for (
const auto& [gate, pin_groups] : structures)
114 for (
const auto* pin_group : pin_groups)
116 std::vector<Net*> nets;
117 for (
const auto* pin : pin_group->get_pins())
121 nets.push_back(gate->get_fan_in_net(pin));
125 nets.push_back(gate->get_fan_out_net(pin));
142 for (
const auto* gate : this->
netlist->
get_gates([structures](
const Gate*
g) { return structures.find(g->get_type()) != structures.end(); }))
144 for (
const auto* pin_group : gate->get_type()->get_pin_groups())
146 std::vector<Net*> nets;
147 for (
const auto* pin : pin_group->get_pins())
151 nets.push_back(gate->get_fan_in_net(pin));
155 nets.push_back(gate->get_fan_out_net(pin));
172 for (
const auto* gate : this->
netlist->
get_gates([structures](
const Gate*
g) { return structures.find(g->get_type()) != structures.end(); }))
174 for (
const auto* pin_group : structures.at(gate->get_type()))
176 std::vector<Net*> nets;
177 for (
const auto* pin : pin_group->get_pins())
181 nets.push_back(gate->get_fan_in_net(pin));
185 nets.push_back(gate->get_fan_out_net(pin));
202 for (
auto* mod : groups)
231 for (
const auto& gate_ids : groups)
233 std::vector<Gate*> gates;
234 std::transform(gate_ids.cbegin(), gate_ids.cend(), std::back_inserter(gates), [
this](
u32 gid) { return this->netlist->get_gate_by_id(gid); });
248 for (
const auto& [_, gates] : groups)
250 std::vector<Gate*> group(gates.cbegin(), gates.cend());
265 this->
gate_types.insert(types.begin(), types.end());
283 std::set<const GateType*> types;
284 std::transform(gate_types_map.begin(), gate_types_map.end(), std::inserter(types, types.begin()), [](
const auto& gt) { return gt.second; });
This file contains the struct that holds all information on a dataflow analysis configuration.
std::unordered_map< std::string, GateType * > get_gate_types(const std::function< bool(const GateType *)> &filter=nullptr) const
bool has_property(GateTypeProperty property) const
const std::vector< Gate * > & get_gates() const
const GateLibrary * get_gate_library() const
Configuration of a dataflow analysis run.
Configuration & with_flip_flops()
Use the default detection configuration for flip-flops.
std::vector< std::vector< Net * > > known_net_groups
Groups of nets that have been identified as word-level datapathes beforehand. Defaults to an empty ve...
std::vector< u32 > expected_sizes
Expected group sizes. Groups of these sizes will be prioritized. Defaults to an empty vector.
Configuration & with_type_consistency(bool enable=true)
Enable type consistency as part of dataflow analysis when deciding whether two gates are allowed to m...
std::set< const GateType * > gate_types
The gate types to be grouped by dataflow analysis. Defaults to an empty set.
std::set< PinType > control_pin_types
The pin types of the pins to be considered control pins. Defaults to an empty set.
Configuration(Netlist *nl)
Construct a new dataflow analysis configuration for the given netlist.
Configuration & with_gate_types(const std::set< const GateType * > &types, bool overwrite=false)
Add the gate types to the set of gate types to be grouped by dataflow analysis.
Configuration & with_control_pin_types(const std::set< PinType > &types, bool overwrite=false)
Set the pin types of the pins to be considered control pins by dataflow analysis.
Configuration & with_stage_identification(bool enable=true)
Enable stage identification as part of dataflow analysis.
Configuration & with_known_groups(const std::vector< Module * > &groups, bool overwrite=false)
Add modules to the set of previously identified word-level groups.
bool enforce_type_consistency
Enforce gate type consistency inside of a group. Defaults to false.
u32 min_group_size
Minimum size of a group. Smaller groups will be penalized during analysis. Defaults to 8.
Configuration & with_expected_sizes(const std::vector< u32 > &sizes)
Set the expected group sizes. Groups of these sizes will be prioritized.
std::vector< std::vector< Gate * > > known_gate_groups
Groups of gates that have already been identified as word-level groups beforehand....
Configuration & with_min_group_size(u32 size)
Set the minimum size of a group. Smaller groups will be penalized during analysis.
bool enable_stages
Enable stage identification as part of dataflow analysis. Defaults to false.
Netlist * netlist
The netlist to be analyzed.
Configuration & with_known_structures(const std::vector< Module * > &structures, bool overwrite=false)
Add modules to the set of previously identified word-level structures.