HAL
configuration.cpp
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2 
8 
9 namespace hal
10 {
11  namespace dataflow
12  {
14  {
15  }
16 
18  {
19  this->min_group_size = size;
20  return *this;
21  }
22 
23  Configuration& Configuration::with_expected_sizes(const std::vector<u32>& sizes)
24  {
25  this->expected_sizes = sizes;
26  return *this;
27  }
28 
29  Configuration& Configuration::with_known_structures(const std::vector<Module*>& structures, bool overwrite)
30  {
31  if (overwrite)
32  {
33  this->known_net_groups.clear();
34  }
35 
36  for (const auto* mod : structures)
37  {
38  for (const auto* pin_group : mod->get_pin_groups())
39  {
40  std::vector<Net*> nets;
41  for (const auto* pin : pin_group->get_pins())
42  {
43  nets.push_back(pin->get_net());
44  }
45  this->known_net_groups.push_back(nets);
46  }
47  }
48 
49  return *this;
50  }
51 
52  Configuration& Configuration::with_known_structures(const std::vector<std::pair<Module*, std::vector<PinGroup<ModulePin>*>>>& structures, bool overwrite)
53  {
54  if (overwrite)
55  {
56  this->known_net_groups.clear();
57  }
58 
59  for (const auto& [_, pin_groups] : structures)
60  {
61  for (const auto* pin_group : pin_groups)
62  {
63  std::vector<Net*> nets;
64  for (const auto* pin : pin_group->get_pins())
65  {
66  nets.push_back(pin->get_net());
67  }
68  this->known_net_groups.push_back(nets);
69  }
70  }
71 
72  return *this;
73  }
74 
75  Configuration& Configuration::with_known_structures(const std::vector<Gate*>& structures, bool overwrite)
76  {
77  if (overwrite)
78  {
79  this->known_net_groups.clear();
80  }
81 
82  for (const auto* gate : structures)
83  {
84  for (const auto* pin_group : gate->get_type()->get_pin_groups())
85  {
86  std::vector<Net*> nets;
87  for (const auto* pin : pin_group->get_pins())
88  {
89  if (pin->get_direction() == PinDirection::input)
90  {
91  nets.push_back(gate->get_fan_in_net(pin));
92  }
93  else if (pin->get_direction() == PinDirection::output)
94  {
95  nets.push_back(gate->get_fan_out_net(pin));
96  }
97  }
98  this->known_net_groups.push_back(nets);
99  }
100  }
101 
102  return *this;
103  }
104 
105  Configuration& Configuration::with_known_structures(const std::vector<std::pair<Gate*, std::vector<PinGroup<GatePin>*>>>& structures, bool overwrite)
106  {
107  if (overwrite)
108  {
109  this->known_net_groups.clear();
110  }
111 
112  for (const auto& [gate, pin_groups] : structures)
113  {
114  for (const auto* pin_group : pin_groups)
115  {
116  std::vector<Net*> nets;
117  for (const auto* pin : pin_group->get_pins())
118  {
119  if (pin->get_direction() == PinDirection::input)
120  {
121  nets.push_back(gate->get_fan_in_net(pin));
122  }
123  else if (pin->get_direction() == PinDirection::output)
124  {
125  nets.push_back(gate->get_fan_out_net(pin));
126  }
127  }
128  this->known_net_groups.push_back(nets);
129  }
130  }
131 
132  return *this;
133  }
134 
135  Configuration& Configuration::with_known_structures(const std::unordered_set<const GateType*>& structures, bool overwrite)
136  {
137  if (overwrite)
138  {
139  this->known_net_groups.clear();
140  }
141 
142  for (const auto* gate : this->netlist->get_gates([structures](const Gate* g) { return structures.find(g->get_type()) != structures.end(); }))
143  {
144  for (const auto* pin_group : gate->get_type()->get_pin_groups())
145  {
146  std::vector<Net*> nets;
147  for (const auto* pin : pin_group->get_pins())
148  {
149  if (pin->get_direction() == PinDirection::input)
150  {
151  nets.push_back(gate->get_fan_in_net(pin));
152  }
153  else if (pin->get_direction() == PinDirection::output)
154  {
155  nets.push_back(gate->get_fan_out_net(pin));
156  }
157  }
158  this->known_net_groups.push_back(nets);
159  }
160  }
161 
162  return *this;
163  }
164 
165  Configuration& Configuration::with_known_structures(const std::unordered_map<const GateType*, std::vector<PinGroup<GatePin>*>>& structures, bool overwrite)
166  {
167  if (overwrite)
168  {
169  this->known_net_groups.clear();
170  }
171 
172  for (const auto* gate : this->netlist->get_gates([structures](const Gate* g) { return structures.find(g->get_type()) != structures.end(); }))
173  {
174  for (const auto* pin_group : structures.at(gate->get_type()))
175  {
176  std::vector<Net*> nets;
177  for (const auto* pin : pin_group->get_pins())
178  {
179  if (pin->get_direction() == PinDirection::input)
180  {
181  nets.push_back(gate->get_fan_in_net(pin));
182  }
183  else if (pin->get_direction() == PinDirection::output)
184  {
185  nets.push_back(gate->get_fan_out_net(pin));
186  }
187  }
188  this->known_net_groups.push_back(nets);
189  }
190  }
191 
192  return *this;
193  }
194 
195  Configuration& Configuration::with_known_groups(const std::vector<Module*>& groups, bool overwrite)
196  {
197  if (overwrite)
198  {
199  this->known_gate_groups.clear();
200  }
201 
202  for (auto* mod : groups)
203  {
204  this->known_gate_groups.push_back(mod->get_gates());
205  }
206 
207  return *this;
208  }
209 
210  Configuration& Configuration::with_known_groups(const std::vector<std::vector<Gate*>>& groups, bool overwrite)
211  {
212  if (overwrite)
213  {
214  this->known_gate_groups = groups;
215  }
216  else
217  {
218  this->known_gate_groups.insert(this->known_gate_groups.end(), groups.begin(), groups.end());
219  }
220 
221  return *this;
222  }
223 
224  Configuration& Configuration::with_known_groups(const std::vector<std::vector<u32>>& groups, bool overwrite)
225  {
226  if (overwrite)
227  {
228  this->known_gate_groups.clear();
229  }
230 
231  for (const auto& gate_ids : groups)
232  {
233  std::vector<Gate*> gates;
234  std::transform(gate_ids.cbegin(), gate_ids.cend(), std::back_inserter(gates), [this](u32 gid) { return this->netlist->get_gate_by_id(gid); });
235  this->known_gate_groups.push_back(gates);
236  }
237 
238  return *this;
239  }
240 
241  Configuration& Configuration::with_known_groups(const std::unordered_map<u32, std::unordered_set<Gate*>>& groups, bool overwrite)
242  {
243  if (overwrite)
244  {
245  this->known_gate_groups.clear();
246  }
247 
248  for (const auto& [_, gates] : groups)
249  {
250  std::vector<Gate*> group(gates.cbegin(), gates.cend());
251  this->known_gate_groups.push_back(group);
252  }
253 
254  return *this;
255  }
256 
257  Configuration& Configuration::with_gate_types(const std::set<const GateType*>& types, bool overwrite)
258  {
259  if (overwrite)
260  {
261  this->gate_types = types;
262  }
263  else
264  {
265  this->gate_types.insert(types.begin(), types.end());
266  }
267 
268  return *this;
269  }
270 
271  Configuration& Configuration::with_gate_types(const std::set<GateTypeProperty>& gate_type_properties, bool overwrite)
272  {
273  auto gate_types_map = this->netlist->get_gate_library()->get_gate_types([gate_type_properties](const GateType* gt) {
274  for (GateTypeProperty p : gate_type_properties)
275  {
276  if (gt->has_property(p))
277  {
278  return true;
279  }
280  }
281  return false;
282  });
283  std::set<const GateType*> types;
284  std::transform(gate_types_map.begin(), gate_types_map.end(), std::inserter(types, types.begin()), [](const auto& gt) { return gt.second; });
285  this->with_gate_types(types, overwrite);
286 
287  return *this;
288  }
289 
290  Configuration& Configuration::with_control_pin_types(const std::set<PinType>& types, bool overwrite)
291  {
292  if (overwrite)
293  {
294  this->control_pin_types = types;
295  }
296  else
297  {
298  this->control_pin_types.insert(types.begin(), types.end());
299  }
300 
301  return *this;
302  }
303 
305  {
306  this->with_gate_types({GateTypeProperty::ff}, true);
308 
309  return *this;
310  }
311 
313  {
314  this->enable_stages = enable;
315  return *this;
316  }
317 
319  {
320  this->enforce_type_consistency = enable;
321  return *this;
322  }
323  } // namespace dataflow
324 } // namespace hal
This file contains the struct that holds all information on a dataflow analysis configuration.
Definition: gate.h:58
std::unordered_map< std::string, GateType * > get_gate_types(const std::function< bool(const GateType *)> &filter=nullptr) const
bool has_property(GateTypeProperty property) const
Definition: gate_type.cpp:101
const std::vector< Gate * > & get_gates() const
Definition: netlist.cpp:204
const GateLibrary * get_gate_library() const
Definition: netlist.cpp:132
quint32 u32
Configuration of a dataflow analysis run.
Definition: configuration.h:61
Configuration & with_flip_flops()
Use the default detection configuration for flip-flops.
std::vector< std::vector< Net * > > known_net_groups
Groups of nets that have been identified as word-level datapathes beforehand. Defaults to an empty ve...
Definition: configuration.h:92
std::vector< u32 > expected_sizes
Expected group sizes. Groups of these sizes will be prioritized. Defaults to an empty vector.
Definition: configuration.h:82
Configuration & with_type_consistency(bool enable=true)
Enable type consistency as part of dataflow analysis when deciding whether two gates are allowed to m...
std::set< const GateType * > gate_types
The gate types to be grouped by dataflow analysis. Defaults to an empty set.
Definition: configuration.h:97
std::set< PinType > control_pin_types
The pin types of the pins to be considered control pins. Defaults to an empty set.
Configuration(Netlist *nl)
Construct a new dataflow analysis configuration for the given netlist.
Configuration & with_gate_types(const std::set< const GateType * > &types, bool overwrite=false)
Add the gate types to the set of gate types to be grouped by dataflow analysis.
Configuration & with_control_pin_types(const std::set< PinType > &types, bool overwrite=false)
Set the pin types of the pins to be considered control pins by dataflow analysis.
Configuration & with_stage_identification(bool enable=true)
Enable stage identification as part of dataflow analysis.
Configuration & with_known_groups(const std::vector< Module * > &groups, bool overwrite=false)
Add modules to the set of previously identified word-level groups.
bool enforce_type_consistency
Enforce gate type consistency inside of a group. Defaults to false.
u32 min_group_size
Minimum size of a group. Smaller groups will be penalized during analysis. Defaults to 8.
Definition: configuration.h:77
Configuration & with_expected_sizes(const std::vector< u32 > &sizes)
Set the expected group sizes. Groups of these sizes will be prioritized.
std::vector< std::vector< Gate * > > known_gate_groups
Groups of gates that have already been identified as word-level groups beforehand....
Definition: configuration.h:87
Configuration & with_min_group_size(u32 size)
Set the minimum size of a group. Smaller groups will be penalized during analysis.
bool enable_stages
Enable stage identification as part of dataflow analysis. Defaults to false.
Netlist * netlist
The netlist to be analyzed.
Definition: configuration.h:72
Configuration & with_known_structures(const std::vector< Module * > &structures, bool overwrite=false)
Add modules to the set of previously identified word-level structures.