hal::resynthesis Namespace Reference

Functions
Result< std::monostate >	decompose_gate (Netlist *nl, Gate *gate, const bool delete_gate=true)
Result< u32 >	decompose_gates_of_type (Netlist *nl, const std::vector< const GateType * > &gate_types)
Result< std::monostate >	resynthesize_gate (Netlist *nl, Gate *gate, GateLibrary *target_gl, const bool delete_gate=true)
Result< u32 >	resynthesize_gates (Netlist *nl, const std::vector< Gate * > &gates, GateLibrary *target_gl)
Result< u32 >	resynthesize_gates_of_type (Netlist *nl, const std::vector< const GateType * > &gate_types, GateLibrary *target_gl)
Result< u32 >	resynthesize_subgraph (Netlist *nl, const std::vector< Gate * > &subgraph, GateLibrary *target_gl)
Result< u32 >	resynthesize_subgraph_of_type (Netlist *nl, const std::vector< const GateType * > &gate_types, GateLibrary *target_gl)
Result< std::monostate >	replace_subgraph_with_netlist (const std::vector< Gate * > &subgraph, const std::unordered_map< Net *, std::vector< Net * >> &global_io_mapping, const Netlist *src_nl, Netlist *dst_nl, const bool delete_subgraph_gates)
Result< std::unique_ptr< Netlist > >	generate_resynth_netlist_for_boolean_functions (const std::unordered_map< std::string, BooleanFunction > &bfs, const std::filesystem::path &genlib_path, GateLibrary *target_gl, const bool optimize_area)

Detailed Description

Re-implements parts of a netlist with a different gate library by resynthesizing their Boolean functions.

Function Documentation

decompose_gate()

Result< std::monostate > hal::resynthesis::decompose_gate	(	Netlist *	nl,
		Gate *	gate,
		const bool	delete_gate = true
	)

Decompose a combinational gate into a small circuit of AND, OR, XOR, and INVERT gates. For each output pin, the resolved Boolean function (only dependent on input pins) is determined. All these Boolean functions are then converted into a netlist using the previously mentioned primitive gates. The target gate is then replaced in the original netlist with the circuit that was just generated. The target gate is only deleted if delete_gate is set to true. Gate replacement will fail if the gate library of the netlist does not contain suitable AND, OR, XOR, and INVERT gate types.

Parameters

[in]	nl	- The netlist to operate on.
[in]	gate	- The gate to decompose.
[in]	delete_gate	- Set true to delete the original gate, false to keep it in the netlist. Defaults to true.

Returns

OK() on success, an error otherwise.

Definition at line 723 of file resynthesis.cpp.

References hal::Netlist::delete_gate(), ERR, ERR_APPEND, hal::Netlist::get_gate_library(), hal::Gate::get_id(), hal::Gate::get_name(), hal::GateType::get_output_pins(), hal::Gate::get_resolved_boolean_function(), hal::Gate::get_type(), and OK.

Referenced by hal::PYBIND11_PLUGIN().

decompose_gates_of_type()

Result< u32 > hal::resynthesis::decompose_gates_of_type	(	Netlist *	nl,
		const std::vector< const GateType * > &	gate_types
	)

Decompose all combinational gates of the specified types into small circuits of AND, OR, XOR, and INVERT gates. For all output pins of each gate, the resolved Boolean function (only dependent on input pins) is determined. All these Boolean functions are then converted into a circuit using the previously mentioned primitive gates. The target gates are then replaced (and thereby deleted) in the original netlist with the circuit that was just generated. Gate replacement will fail if the gate library of the netlist does not contain suitable AND, OR, XOR, and INVERT gate types.

Parameters

[in]	nl	- The netlist to operate on.
[in]	gate_types	- The gate types to be decomposed.

Returns

OK() and the number of decomposed gates on success, an error otherwise.

Definition at line 768 of file resynthesis.cpp.

References hal::c_lut, hal::Netlist::delete_gate(), ERR, ERR_APPEND, hal::Netlist::get_gate_library(), hal::Netlist::get_gates(), hal::Gate::get_id(), hal::Gate::get_init_data(), hal::Gate::get_name(), hal::GateType::get_name(), hal::GateType::get_output_pins(), hal::Gate::get_resolved_boolean_function(), hal::Gate::get_type(), and OK.

Referenced by hal::PYBIND11_PLUGIN().

generate_resynth_netlist_for_boolean_functions()

Result< std::unique_ptr< Netlist > > hal::resynthesis::generate_resynth_netlist_for_boolean_functions	(	const std::unordered_map< std::string, BooleanFunction > &	bfs,
		const std::filesystem::path &	genlib_path,
		GateLibrary *	target_gl,
		const bool	optimize_area
	)

Definition at line 1268 of file resynthesis.cpp.

References hal::LogManager::activate_channel(), hal::LogManager::deactivate_channel(), ERR, ERR_APPEND, hal::LogManager::get_instance(), hal::utils::get_unique_temp_directory(), hal::netlist_factory::load_netlist(), net, OK, and hal::yosys::query_binary_path().

replace_subgraph_with_netlist()

Result< std::monostate > hal::resynthesis::replace_subgraph_with_netlist	(	const std::vector< Gate * > &	subgraph,
		const std::unordered_map< Net *, std::vector< Net * >> &	global_io_mapping,
		const Netlist *	src_nl,
		Netlist *	dst_nl,
		const bool	delete_subgraph_gates
	)

Definition at line 1118 of file resynthesis.cpp.

References hal::Net::add_destination(), hal::Net::add_source(), hal::NetlistModificationDecorator::connect_nets(), hal::Netlist::create_gate(), hal::Netlist::create_net(), ERR, ERR_APPEND, hal::Netlist::get_gate_library(), hal::GateLibrary::get_gate_type_by_name(), hal::Netlist::get_gates(), hal::Netlist::get_gnd_gates(), hal::Net::get_id(), hal::Net::get_name(), hal::Netlist::get_nets(), hal::Netlist::get_vcc_gates(), log_warning, OK, and hal::Net::set_name().

Referenced by resynthesize_subgraph().

resynthesize_gate()

Result< std::monostate > hal::resynthesis::resynthesize_gate	(	Netlist *	nl,
		Gate *	gate,
		GateLibrary *	target_gl,
		const bool	delete_gate = true
	)

Re-synthesize a combinational gate by calling Yosys on a functional description of the gate using a reduced gate library. For each output pin, the resolved Boolean function (only dependent on input pins) is determined. All these Boolean functions are then written to an HDL file that is functionally equivalent to the target gate. This file is fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. The provided gate library should be a subset of the gate library that was used to parse the netlist. The target gate is then replaced in the original netlist with the circuit that was just generated. The target gate is only deleted if delete_gate is set to true.

Parameters

[in]	nl	- The netlist to operate on.
[in]	gate	- The gate to re-synthesize.
[in]	target_gl	- The gate library that is a subset of the gate library used to parse the netlist.
[in]	delete_gate	- Set true to delete the original gate, false to keep it in the netlist. Defaults to true.

Returns

OK() on success, an error otherwise.

Definition at line 857 of file resynthesis.cpp.

References hal::Netlist::delete_gate(), ERR, ERR_APPEND, hal::Gate::get_id(), hal::Gate::get_name(), hal::GateLibrary::get_name(), hal::utils::get_unique_temp_directory(), OK, and hal::gate_library_manager::save().

Referenced by hal::PYBIND11_PLUGIN().

resynthesize_gates()

Result< u32 > hal::resynthesis::resynthesize_gates	(	Netlist *	nl,
		const std::vector< Gate * > &	gates,
		GateLibrary *	target_gl
	)

Re-synthesize all specified combinational gates by calling Yosys on a functional description of the gates using a reduced gate library. For all output pins of each gate, the resolved Boolean function (only dependent on input pins) is determined. All Boolean functions of a gate are then written to an HDL file that is functionally equivalent to the gate. These files are fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. The provided gate library should be a subset of the gate library that was used to parse the netlist. The gates are then replaced in the original netlist with the circuits that were just generated. This process is repeated for every gate, hence they are re-synthesized in isolation.

Parameters

[in]	nl	- The netlist to operate on.
[in]	gates	- The gates to re-synthesize.
[in]	target_gl	- The gate library that is a subset of the gate library used to parse the netlist.

Returns

OK() and the number of re-synthesized gates on success, an error otherwise.

Definition at line 914 of file resynthesis.cpp.

References hal::c_lut, hal::Netlist::delete_gate(), ERR, ERR_APPEND, hal::GateLibrary::get_name(), hal::utils::get_unique_temp_directory(), OK, and hal::gate_library_manager::save().

Referenced by hal::PYBIND11_PLUGIN(), and resynthesize_gates_of_type().

resynthesize_gates_of_type()

Result< u32 > hal::resynthesis::resynthesize_gates_of_type	(	Netlist *	nl,
		const std::vector< const GateType * > &	gate_types,
		GateLibrary *	target_gl
	)

Re-synthesize all combinational gates of the specified types by calling Yosys on a functional description of the gates using a reduced gate library. For all output pins of each gate, the resolved Boolean function (only dependent on input pins) is determined. All Boolean functions of a gate are then written to an HDL file that is functionally equivalent to the gate. These files are fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. The provided gate library should be a subset of the gate library that was used to parse the netlist. The gates are then replaced in the original netlist with the circuits that were just generated. This process is repeated for every gate, hence they are re-synthesized in isolation.

Parameters

[in]	nl	- The netlist to operate on.
[in]	gate_types	- The gate types to be re-synthesized.
[in]	target_gl	- The gate library that is a subset of the gate library used to parse the netlist.

Returns

OK() and the number of re-synthesized gates on success, an error otherwise.

Definition at line 1002 of file resynthesis.cpp.

References hal::Netlist::get_gates(), and resynthesize_gates().

Referenced by hal::PYBIND11_PLUGIN().

resynthesize_subgraph()

Result< u32 > hal::resynthesis::resynthesize_subgraph	(	Netlist *	nl,
		const std::vector< Gate * > &	subgraph,
		GateLibrary *	target_gl
	)

Re-synthesize the combinational gates of the subgraph by calling Yosys on a Verilog netlist representation of the subgraph using a reduced gate library. All gates of the subgraph are written to a Verilog netlist file which is then fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. The provided gate library should be a subset of the gate library that was used to parse the netlist. The gates are then replaced in the original netlist with the circuit that was just generated.

Parameters

[in]	nl	- The netlist to operate on.
[in]	subgraph	- The subgraph to re-synthesize.
[in]	target_gl	- The gate library that is a subset of the gate library used to parse the netlist.

Returns

OK() and the number of re-synthesized gates on success, an error otherwise.

Definition at line 1021 of file resynthesis.cpp.

References ERR, ERR_APPEND, hal::GateLibrary::get_name(), hal::Netlist::get_nets(), hal::utils::get_unique_temp_directory(), OK, replace_subgraph_with_netlist(), and hal::gate_library_manager::save().

Referenced by hal::PYBIND11_PLUGIN(), and resynthesize_subgraph_of_type().

resynthesize_subgraph_of_type()

Result< u32 > hal::resynthesis::resynthesize_subgraph_of_type	(	Netlist *	nl,
		const std::vector< const GateType * > &	gate_types,
		GateLibrary *	target_gl
	)

Re-synthesize the combinational gates of the specified types as a subgraph by calling Yosys on a Verilog netlist representation of the subgraph induced by these gates using a reduced gate library. All gates of the subgraph are written to a Verilog netlist file which is then fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. The provided gate library should be a subset of the gate library that was used to parse the netlist. The gates are then replaced in the original netlist with the circuit that was just generated.

Parameters

[in]	nl	- The netlist to operate on.
[in]	gate_types	- The gate types to be re-synthesized.
[in]	target_gl	- The gate library that is a subset of the gate library used to parse the netlist.

Returns

OK() and the number of re-synthesized gates on success, an error otherwise.

Definition at line 1103 of file resynthesis.cpp.

References hal::Netlist::get_gates(), and resynthesize_subgraph().

Referenced by hal::PYBIND11_PLUGIN().