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HAL
v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
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Functions | |
| bool | convert_gate_library_to_verilog (const Netlist *nl, const std::filesystem::path verilator_sim_path, const std::filesystem::path model_path="") |
| std::set< std::string > | get_provided_models (const std::filesystem::path model_path, const std::filesystem::path gate_definition_path) |
| std::unordered_map< GateType *, std::string > | get_gate_gate_types_from_netlist (const Netlist *nl) |
| std::vector< std::string > | get_parameters_for_gate (const GateType *gt) |
| std::string | get_name_for_gate_type (const GateType *gt) |
| std::string | get_prologue_for_gate_type (const GateType *gt) |
| Result< std::string > | verilog_function_printer (const BooleanFunction::Node &node, std::vector< std::string > &&operands) |
| std::string | get_function_for_gate (const GateType *gt) |
| std::string | get_function_for_lut (const GateType *gt) |
| std::string | get_function_for_combinational_gate (const GateType *gt) |
| std::string | get_function_for_ff (const GateType *gt) |
| std::string | get_function_for_latch (const GateType *gt) |
| std::string | get_epilogue_for_gate_type () |
Translates a HAL netlist and its gate library into the Verilog sources that Verilator compiles.
| bool hal::verilator::converter::convert_gate_library_to_verilog | ( | const Netlist * | nl, |
| const std::filesystem::path | verilator_sim_path, | ||
| const std::filesystem::path | model_path = "" |
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| ) |
Generate verilog simulation models based on gate library provided in HAL.
| [in] | nl | - Netlist for which the models shall be created |
| [in] | verilator_sim_path | - Path where the verilator simulation files are going to be stored. |
| [in] | model_path | - Path where the provided models are located. |
true if the model gerneration was successful, false otherwise. Definition at line 29 of file converter.cpp.
References get_epilogue_for_gate_type(), get_function_for_gate(), get_gate_gate_types_from_netlist(), hal::Netlist::get_gate_library(), hal::GateLibrary::get_name(), get_prologue_for_gate_type(), get_provided_models(), log_debug, log_error, and log_info.
Referenced by hal::PYBIND11_PLUGIN(), and hal::verilator::VerilatorEngine::setSimulationInput().
| std::string hal::verilator::converter::get_epilogue_for_gate_type | ( | ) |
Generates the epilogue for the gate type.
Definition at line 365 of file converter.cpp.
Referenced by convert_gate_library_to_verilog().
| std::string hal::verilator::converter::get_function_for_combinational_gate | ( | const GateType * | gt | ) |
Generates the functionality for the combinational gate.
| [in] | gt | - The gate type to create the function for. |
Definition at line 19 of file combinational_function.cpp.
References hal::GateType::get_boolean_functions(), hal::BasePin< T >::get_group(), hal::BasePin< T >::get_name(), hal::GateType::get_pin_by_name(), hal::BooleanFunction::get_variable_names(), hal::BooleanFunction::substitute(), hal::BooleanFunction::to_string(), and verilog_function_printer().
Referenced by get_function_for_gate().
| std::string hal::verilator::converter::get_function_for_ff | ( | const GateType * | gt | ) |
Generates the functionality for the FF gate type.
| [in] | gt | - The gate type to create the function for. |
Definition at line 23 of file ff_function.cpp.
References hal::clock, hal::GateType::get_boolean_function(), hal::GateTypeComponent::get_component_as(), hal::GateType::get_component_as(), hal::GateType::get_name(), hal::StateComponent::get_neg_state_identifier(), hal::GateType::get_output_pins(), hal::GateType::get_pins(), hal::StateComponent::get_state_identifier(), hal::BasePin< T >::get_type(), hal::H, hal::BooleanFunction::is_empty(), hal::L, log_error, hal::N, hal::T, hal::BooleanFunction::to_string(), verilog_function_printer(), and hal::X.
Referenced by get_function_for_gate().
| std::string hal::verilator::converter::get_function_for_gate | ( | const GateType * | gt | ) |
Generates the functionality for the gate type.
| [in] | gt | - The gate type to create the function for. |
Definition at line 338 of file converter.cpp.
References hal::c_buffer, hal::c_lut, hal::combinational, hal::ff, get_function_for_combinational_gate(), get_function_for_ff(), get_function_for_latch(), get_function_for_lut(), hal::GateType::has_property(), and hal::latch.
Referenced by convert_gate_library_to_verilog().
| std::string hal::verilator::converter::get_function_for_latch | ( | const GateType * | gt | ) |
Generates the functionality for the latch gate type.
| [in] | gt | - The gate type to create the function for. |
Definition at line 22 of file latch_function.cpp.
References hal::enable, hal::GateType::get_boolean_function(), hal::GateTypeComponent::get_component_as(), hal::GateType::get_component_as(), hal::GateType::get_name(), hal::GateType::get_output_pins(), hal::H, hal::L, log_error, hal::N, hal::T, verilog_function_printer(), and hal::X.
Referenced by get_function_for_gate().
| std::string hal::verilator::converter::get_function_for_lut | ( | const GateType * | gt | ) |
Generates the functionality for the LUT gate type.
| [in] | gt | - The gate type to create the function for. |
Definition at line 22 of file lut_function.cpp.
References hal::GateType::get_component_as(), hal::InitComponent::get_init_identifiers(), hal::GateType::get_input_pins(), hal::GateType::get_name(), hal::GateType::get_output_pins(), hal::InitComponent::is_class_of(), log_debug, and log_error.
Referenced by get_function_for_gate().
| std::unordered_map< GateType *, std::string > hal::verilator::converter::get_gate_gate_types_from_netlist | ( | const Netlist * | nl | ) |
Get all used gate types in netlist mapped to the appropriate variable name.
| [in] | nl | - Netlist for which the models shall be created |
Definition at line 144 of file converter.cpp.
References hal::Netlist::get_gates(), and get_name_for_gate_type().
Referenced by hal::verilator::cleanup_gate_type_names(), and convert_gate_library_to_verilog().
| std::string hal::verilator::converter::get_name_for_gate_type | ( | const GateType * | gt | ) |
Get the gate type name cleaned from characters that are not elegible in a variable name
| gt | - The gate type to get the name from |
Definition at line 156 of file converter.cpp.
References hal::GateType::get_name().
Referenced by get_gate_gate_types_from_netlist().
| std::vector< std::string > hal::verilator::converter::get_parameters_for_gate | ( | const GateType * | gt | ) |
Generate the parameters function for the simulation model of the gate.
| [in] | gt | - The gate type to create the parameters for. |
Definition at line 177 of file converter.cpp.
References hal::c_lut, hal::ff, hal::GateType::get_component_as(), hal::InitComponent::get_init_identifiers(), hal::GateType::get_input_pins(), hal::GateType::get_name(), hal::GateType::has_property(), hal::InitComponent::is_class_of(), hal::latch, and log_error.
Referenced by get_prologue_for_gate_type().
| std::string hal::verilator::converter::get_prologue_for_gate_type | ( | const GateType * | gt | ) |
Generates the prologue for the simulation model.
| [in] | gt | - The gate type to create the parameters for. |
Definition at line 236 of file converter.cpp.
References direction, hal::enum_to_string(), hal::GateType::get_name(), get_parameters_for_gate(), and hal::GateType::get_pins().
Referenced by convert_gate_library_to_verilog().
| std::set< std::string > hal::verilator::converter::get_provided_models | ( | const std::filesystem::path | model_path, |
| const std::filesystem::path | gate_definition_path | ||
| ) |
Gets the list of provided models, for which no simulation models have to generated. The function also copies the provided models to the simulation folder.
| [in] | model_path | - Path where the provided models are located. |
| [in] | gate_definition_path | - Path where the models shall be copied to. |
Definition at line 103 of file converter.cpp.
References log_info, log_warning, and hal::utils::replace().
Referenced by convert_gate_library_to_verilog().
| Result< std::string > hal::verilator::converter::verilog_function_printer | ( | const BooleanFunction::Node & | node, |
| std::vector< std::string > && | operands | ||
| ) |
Translate a given Boolean function node into a human-readable string in Verilog format.
| [in] | node | The node of a Boolean function. |
| [in] | operands | The operands of the node . |
Definition at line 304 of file converter.cpp.
References hal::BooleanFunction::NodeType::And, hal::BooleanFunction::Node::constant, hal::BooleanFunction::NodeType::Constant, hal::enum_to_string(), ERR, hal::BooleanFunction::Node::get_arity(), hal::BooleanFunction::Node::index, hal::BooleanFunction::NodeType::Index, hal::BooleanFunction::NodeType::Not, OK, hal::BooleanFunction::NodeType::Or, hal::BooleanFunction::Node::type, hal::BooleanFunction::Node::variable, hal::BooleanFunction::NodeType::Variable, and hal::BooleanFunction::NodeType::Xor.
Referenced by get_function_for_combinational_gate(), get_function_for_ff(), and get_function_for_latch().