HAL  v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
hal::verilator::converter Namespace Reference

Functions

bool convert_gate_library_to_verilog (const Netlist *nl, const std::filesystem::path verilator_sim_path, const std::filesystem::path model_path="")
 
std::set< std::string > get_provided_models (const std::filesystem::path model_path, const std::filesystem::path gate_definition_path)
 
std::unordered_map< GateType *, std::string > get_gate_gate_types_from_netlist (const Netlist *nl)
 
std::vector< std::string > get_parameters_for_gate (const GateType *gt)
 
std::string get_name_for_gate_type (const GateType *gt)
 
std::string get_prologue_for_gate_type (const GateType *gt)
 
Result< std::string > verilog_function_printer (const BooleanFunction::Node &node, std::vector< std::string > &&operands)
 
std::string get_function_for_gate (const GateType *gt)
 
std::string get_function_for_lut (const GateType *gt)
 
std::string get_function_for_combinational_gate (const GateType *gt)
 
std::string get_function_for_ff (const GateType *gt)
 
std::string get_function_for_latch (const GateType *gt)
 
std::string get_epilogue_for_gate_type ()
 

Detailed Description

Translates a HAL netlist and its gate library into the Verilog sources that Verilator compiles.

Function Documentation

◆ convert_gate_library_to_verilog()

bool hal::verilator::converter::convert_gate_library_to_verilog ( const Netlist nl,
const std::filesystem::path  verilator_sim_path,
const std::filesystem::path  model_path = "" 
)

Generate verilog simulation models based on gate library provided in HAL.

Parameters
[in]nl- Netlist for which the models shall be created
[in]verilator_sim_path- Path where the verilator simulation files are going to be stored.
[in]model_path- Path where the provided models are located.
Returns
true if the model gerneration was successful, false otherwise.

Definition at line 29 of file converter.cpp.

References get_epilogue_for_gate_type(), get_function_for_gate(), get_gate_gate_types_from_netlist(), hal::Netlist::get_gate_library(), hal::GateLibrary::get_name(), get_prologue_for_gate_type(), get_provided_models(), log_debug, log_error, and log_info.

Referenced by hal::PYBIND11_PLUGIN(), and hal::verilator::VerilatorEngine::setSimulationInput().

◆ get_epilogue_for_gate_type()

std::string hal::verilator::converter::get_epilogue_for_gate_type ( )

Generates the epilogue for the gate type.

Returns
The epilogue for the gate for the simulation model.

Definition at line 365 of file converter.cpp.

Referenced by convert_gate_library_to_verilog().

◆ get_function_for_combinational_gate()

std::string hal::verilator::converter::get_function_for_combinational_gate ( const GateType gt)

Generates the functionality for the combinational gate.

Parameters
[in]gt- The gate type to create the function for.
Returns
The function of the combinational gate for the simulation model.

Definition at line 19 of file combinational_function.cpp.

References hal::GateType::get_boolean_functions(), hal::BasePin< T >::get_group(), hal::BasePin< T >::get_name(), hal::GateType::get_pin_by_name(), hal::BooleanFunction::get_variable_names(), hal::BooleanFunction::substitute(), hal::BooleanFunction::to_string(), and verilog_function_printer().

Referenced by get_function_for_gate().

◆ get_function_for_ff()

std::string hal::verilator::converter::get_function_for_ff ( const GateType gt)

◆ get_function_for_gate()

std::string hal::verilator::converter::get_function_for_gate ( const GateType gt)

Generates the functionality for the gate type.

Parameters
[in]gt- The gate type to create the function for.
Returns
The function of the gate for the simulation model.

Definition at line 338 of file converter.cpp.

References hal::c_buffer, hal::c_lut, hal::combinational, hal::ff, get_function_for_combinational_gate(), get_function_for_ff(), get_function_for_latch(), get_function_for_lut(), hal::GateType::has_property(), and hal::latch.

Referenced by convert_gate_library_to_verilog().

◆ get_function_for_latch()

std::string hal::verilator::converter::get_function_for_latch ( const GateType gt)

Generates the functionality for the latch gate type.

Parameters
[in]gt- The gate type to create the function for.
Returns
The function of the latch gate for the simulation model.

Definition at line 22 of file latch_function.cpp.

References hal::enable, hal::GateType::get_boolean_function(), hal::GateTypeComponent::get_component_as(), hal::GateType::get_component_as(), hal::GateType::get_name(), hal::GateType::get_output_pins(), hal::H, hal::L, log_error, hal::N, hal::T, verilog_function_printer(), and hal::X.

Referenced by get_function_for_gate().

◆ get_function_for_lut()

std::string hal::verilator::converter::get_function_for_lut ( const GateType gt)

Generates the functionality for the LUT gate type.

Parameters
[in]gt- The gate type to create the function for.
Returns
The function of the LUT gate for the simulation model.

Definition at line 22 of file lut_function.cpp.

References hal::GateType::get_component_as(), hal::InitComponent::get_init_identifiers(), hal::GateType::get_input_pins(), hal::GateType::get_name(), hal::GateType::get_output_pins(), hal::InitComponent::is_class_of(), log_debug, and log_error.

Referenced by get_function_for_gate().

◆ get_gate_gate_types_from_netlist()

std::unordered_map< GateType *, std::string > hal::verilator::converter::get_gate_gate_types_from_netlist ( const Netlist nl)

Get all used gate types in netlist mapped to the appropriate variable name.

Parameters
[in]nl- Netlist for which the models shall be created
Returns
Map of used gate types and variable names.

Definition at line 144 of file converter.cpp.

References hal::Netlist::get_gates(), and get_name_for_gate_type().

Referenced by hal::verilator::cleanup_gate_type_names(), and convert_gate_library_to_verilog().

◆ get_name_for_gate_type()

std::string hal::verilator::converter::get_name_for_gate_type ( const GateType gt)

Get the gate type name cleaned from characters that are not elegible in a variable name

Parameters
gt- The gate type to get the name from
Returns
String with gate name suitable as variable name

Definition at line 156 of file converter.cpp.

References hal::GateType::get_name().

Referenced by get_gate_gate_types_from_netlist().

◆ get_parameters_for_gate()

std::vector< std::string > hal::verilator::converter::get_parameters_for_gate ( const GateType gt)

Generate the parameters function for the simulation model of the gate.

Parameters
[in]gt- The gate type to create the parameters for.
Returns
Vector of all parameters that the gate type has.

Definition at line 177 of file converter.cpp.

References hal::c_lut, hal::ff, hal::GateType::get_component_as(), hal::InitComponent::get_init_identifiers(), hal::GateType::get_input_pins(), hal::GateType::get_name(), hal::GateType::has_property(), hal::InitComponent::is_class_of(), hal::latch, and log_error.

Referenced by get_prologue_for_gate_type().

◆ get_prologue_for_gate_type()

std::string hal::verilator::converter::get_prologue_for_gate_type ( const GateType gt)

Generates the prologue for the simulation model.

Parameters
[in]gt- The gate type to create the parameters for.
Returns
The prologue for the simulation model.

Definition at line 236 of file converter.cpp.

References direction, hal::enum_to_string(), hal::GateType::get_name(), get_parameters_for_gate(), and hal::GateType::get_pins().

Referenced by convert_gate_library_to_verilog().

◆ get_provided_models()

std::set< std::string > hal::verilator::converter::get_provided_models ( const std::filesystem::path  model_path,
const std::filesystem::path  gate_definition_path 
)

Gets the list of provided models, for which no simulation models have to generated. The function also copies the provided models to the simulation folder.

Parameters
[in]model_path- Path where the provided models are located.
[in]gate_definition_path- Path where the models shall be copied to.
Returns
Set of provided gate types.

Definition at line 103 of file converter.cpp.

References log_info, log_warning, and hal::utils::replace().

Referenced by convert_gate_library_to_verilog().

◆ verilog_function_printer()

Result< std::string > hal::verilator::converter::verilog_function_printer ( const BooleanFunction::Node node,
std::vector< std::string > &&  operands 
)