HAL  v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
hal::verilator Namespace Reference

Namespaces

 converter
 

Classes

class  VerilatorEngine
 
class  VerilatorEngineFactory
 

Functions

const std::string get_testbench_cpp_template ()
 
void remove_unwanted_parameters_from_netlist (Netlist *nl)
 
std::string escape_net_name (std::string net_name)
 
void cleanup_gate_type_names (const Netlist *nl, const std::filesystem::path &netlist_verilog)
 

Detailed Description

Simulates a netlist by translating it into Verilog and running it through Verilator.

Function Documentation

◆ cleanup_gate_type_names()

void hal::verilator::cleanup_gate_type_names ( const Netlist nl,
const std::filesystem::path &  netlist_verilog 
)

◆ escape_net_name()

std::string hal::verilator::escape_net_name ( std::string  net_name)

Definition at line 72 of file verilator.cpp.

References hal::utils::replace().

◆ get_testbench_cpp_template()

const std::string hal::verilator::get_testbench_cpp_template ( )

Definition at line 37 of file templates.h.

◆ remove_unwanted_parameters_from_netlist()