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HAL
v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
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Namespaces | |
| converter | |
Classes | |
| class | VerilatorEngine |
| class | VerilatorEngineFactory |
Functions | |
| const std::string | get_testbench_cpp_template () |
| void | remove_unwanted_parameters_from_netlist (Netlist *nl) |
| std::string | escape_net_name (std::string net_name) |
| void | cleanup_gate_type_names (const Netlist *nl, const std::filesystem::path &netlist_verilog) |
Simulates a netlist by translating it into Verilog and running it through Verilator.
| void hal::verilator::cleanup_gate_type_names | ( | const Netlist * | nl, |
| const std::filesystem::path & | netlist_verilog | ||
| ) |
Definition at line 84 of file verilator.cpp.
References hal::verilator::converter::get_gate_gate_types_from_netlist().
Referenced by hal::verilator::VerilatorEngine::setSimulationInput().
| std::string hal::verilator::escape_net_name | ( | std::string | net_name | ) |
Definition at line 72 of file verilator.cpp.
References hal::utils::replace().
| const std::string hal::verilator::get_testbench_cpp_template | ( | ) |
Definition at line 37 of file templates.h.
| void hal::verilator::remove_unwanted_parameters_from_netlist | ( | Netlist * | nl | ) |
Definition at line 31 of file verilator.cpp.
References hal::c_lut, hal::combinational, hal::GateTypeComponent::get_component_as(), hal::Netlist::get_gate_library(), hal::Netlist::get_gates(), hal::InitComponent::get_init_category(), hal::InitComponent::get_init_identifiers(), and hal::InitComponent::is_class_of().
Referenced by hal::verilator::VerilatorEngine::setSimulationInput().