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HAL
v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
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#include "netlist_simulator/netlist_simulator.h"#include "hal_core/netlist/gate_library/gate_type_component/ff_component.h"#include "hal_core/netlist/gate_library/gate_type_component/init_component.h"#include "hal_core/netlist/netlist.h"#include "hal_core/utilities/log.h"#include "netlist_simulator/simulation_utils.h"#include "netlist_simulator_controller/simulation_input.h"#include <algorithm>#include <chrono>#include <ctime>#include <fstream>#include <iomanip>#include <sstream>#include <unordered_map>
Go to the source code of this file.
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| hal | |
Macros | |
| #define | measure_block_time(X) |
| #define measure_block_time | ( | X | ) |
Definition at line 20 of file netlist_simulator.cpp.