HAL  v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
netlist_simulator.h
Go to the documentation of this file.
1 // MIT License
2 //
3 // Copyright (c) 2019 Ruhr University Bochum, Chair for Embedded Security. All Rights reserved.
4 // Copyright (c) 2019 Marc Fyrbiak, Sebastian Wallat, Max Hoffmann ("ORIGINAL AUTHORS"). All rights reserved.
5 // Copyright (c) 2021 Max Planck Institute for Security and Privacy. All Rights reserved.
6 // Copyright (c) 2021 Jörn Langheinrich, Julian Speith, Nils Albartus, René Walendy, Simon Klix ("ORIGINAL AUTHORS"). All Rights reserved.
7 //
8 // Permission is hereby granted, free of charge, to any person obtaining a copy
9 // of this software and associated documentation files (the "Software"), to deal
10 // in the Software without restriction, including without limitation the rights
11 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 // copies of the Software, and to permit persons to whom the Software is
13 // furnished to do so, subject to the following conditions:
14 //
15 // The above copyright notice and this permission notice shall be included in all
16 // copies or substantial portions of the Software.
17 //
18 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 // SOFTWARE.
25 
26 #pragma once
27 
28 #include "hal_core/netlist/gate.h"
31 #include "hal_core/netlist/net.h"
34 
35 #include <map>
36 #include <unordered_set>
37 
38 namespace hal
39 {
40  class SimulationInput;
41 
46  {
48 
49  public:
55  const std::unordered_set<Gate*>& get_gates() const;
56 
63  void set_input(const Net* net, BooleanFunction::Value value);
64 
72  void initialize_sequential_gates(const std::function<bool(const Gate*)>& filter = nullptr);
73 
82  void initialize_sequential_gates(BooleanFunction::Value value, const std::function<bool(const Gate*)>& filter = nullptr);
83 
91  [[deprecated("Will be removed in a future version. Use initialize_sequential_gates() instead.")]] void load_initial_values(BooleanFunction::Value value);
92 
99  [[deprecated("Will be removed in a future version. Use initialize_sequential_gates() instead.")]] void load_initial_values_from_netlist();
100 
105  void initialize();
106 
114  void simulate(u64 picoseconds);
115 
117  {
118  return mSimulationInput;
119  }
120 
125  void reset();
126 
134 
140  const Simulation& get_simulation_state() const;
141 
149  void set_iteration_timeout(u64 iterations);
150 
156  u64 get_simulation_timeout() const;
157 
167  bool generate_vcd(const std::filesystem::path& path, u32 start_time, u32 end_time, std::set<const Net*> nets = {}) const;
168 
175  std::vector<WaveEvent> get_simulation_events(u32 netId) const override;
176 
177  bool inputEvent(const SimulationInputNetEvent& netEv) override;
178 
179  private:
181 
185  struct SimulationGate
186  {
187  const Gate* m_gate;
188  std::vector<GatePin*> m_input_pins;
189  std::vector<const Net*> m_input_nets;
190  std::unordered_map<std::string, BooleanFunction::Value> m_input_values;
191 
192  SimulationGate(const Gate* gate);
193  virtual ~SimulationGate() = default;
194 
195  virtual bool simulate(const Simulation& simulation, const WaveEvent& event, std::map<std::pair<const Net*, u64>, BooleanFunction::Value>& new_events) = 0;
196  };
197 
201  struct SimulationGateCombinational : public SimulationGate
202  {
203  std::vector<GatePin*> m_output_pins;
204  std::vector<const Net*> m_output_nets;
205  std::unordered_map<const Net*, BooleanFunction> m_functions;
206 
207  SimulationGateCombinational(const Gate* gate);
208 
209  bool simulate(const Simulation& simulation, const WaveEvent& event, std::map<std::pair<const Net*, u64>, BooleanFunction::Value>& new_events) override;
210  };
211 
215  struct SimulationGateSequential : public SimulationGate
216  {
217  SimulationGateSequential(const Gate* gate);
218 
219  virtual void initialize(std::map<const Net*, BooleanFunction::Value>& new_events, bool from_netlist, BooleanFunction::Value value) = 0;
220  virtual bool simulate(const Simulation& simulation, const WaveEvent& event, std::map<std::pair<const Net*, u64>, BooleanFunction::Value>& new_events) = 0;
221  virtual void clock(const u64 current_time, std::map<std::pair<const Net*, u64>, BooleanFunction::Value>& new_events) = 0;
222  };
223 
227  struct SimulationGateFF : public SimulationGateSequential
228  {
229  BooleanFunction m_clock_func;
230  BooleanFunction m_clear_func;
231  BooleanFunction m_preset_func;
232  BooleanFunction m_next_state_func;
233  std::vector<const Net*> m_state_output_nets;
234  std::vector<const Net*> m_state_inverted_output_nets;
235  std::vector<const Net*> m_clock_nets;
236  AsyncSetResetBehavior m_sr_behavior_out;
237  AsyncSetResetBehavior m_sr_behavior_out_inverted;
238  BooleanFunction::Value m_output;
239  BooleanFunction::Value m_inv_output;
240 
241  SimulationGateFF(const Gate* gate);
242 
243  void initialize(std::map<const Net*, BooleanFunction::Value>& new_events, bool from_netlist, BooleanFunction::Value value) override;
244  bool simulate(const Simulation& simulation, const WaveEvent& event, std::map<std::pair<const Net*, u64>, BooleanFunction::Value>& new_events) override;
245  void clock(const u64 current_time, std::map<std::pair<const Net*, u64>, BooleanFunction::Value>& new_events) override;
246  };
247 
251  struct SimulationGateRAM : public SimulationGateSequential
252  {
256  struct Port
257  {
258  const Net* clock_net;
261  bool is_write;
262 
263  std::vector<GatePin*> address_pins;
264  std::vector<GatePin*> data_pins;
265  };
266 
267  std::vector<Port> m_ports;
268  std::vector<u64> m_data;
269  u32 m_bit_size;
270  std::vector<size_t> m_clocked_read_ports;
271  std::vector<size_t> m_clocked_write_ports;
272 
273  SimulationGateRAM(const Gate* gate);
274 
275  void initialize(std::map<const Net*, BooleanFunction::Value>& new_events, bool from_netlist, BooleanFunction::Value value) override;
276  bool simulate(const Simulation& simulation, const WaveEvent& event, std::map<std::pair<const Net*, u64>, BooleanFunction::Value>& new_events) override;
277  void clock(const u64 current_time, std::map<std::pair<const Net*, u64>, BooleanFunction::Value>& new_events) override;
278  };
279 
280  bool m_is_initialized = false;
281  std::vector<std::tuple<bool, BooleanFunction::Value, const std::function<bool(const Gate*)>>> m_init_seq_gates;
282 
283  u64 m_current_time = 0;
284  std::vector<WaveEvent> m_event_queue;
285  Simulation m_simulation;
286  u64 m_timeout_iterations = 10000000ul;
287  u64 m_id_counter = 0;
288 
289  std::unordered_map<const Net*, std::vector<std::pair<SimulationGate*, std::vector<const GatePin*>>>> m_successors;
290  std::vector<std::unique_ptr<SimulationGate>> m_sim_gates;
291  std::vector<SimulationGate*> m_sim_gates_raw;
292 
293  NetlistSimulator(const std::string& nam);
294  void compute_input_nets();
295  void compute_output_nets();
296  void prepare_clock_events(u64 nanoseconds);
297  void process_events(u64 timeout);
298 
299  BooleanFunction::Value process_clear_preset_behavior(AsyncSetResetBehavior behavior, BooleanFunction::Value previous_output);
300  };
301 
306  {
307  public:
309  {
310  ;
311  }
312  SimulationEngine* createEngine() const override;
313  };
314 } // namespace hal
Value
represents the type of the node
Definition: gate.h:58
Definition: net.h:58
SimulationEngine * createEngine() const override
bool inputEvent(const SimulationInputNetEvent &netEv) override
std::vector< WaveEvent > get_simulation_events(u32 netId) const override
void set_iteration_timeout(u64 iterations)
void simulate(u64 picoseconds)
void initialize_sequential_gates(const std::function< bool(const Gate *)> &filter=nullptr)
void set_simulation_state(const Simulation &state)
void load_initial_values(BooleanFunction::Value value)
const Simulation & get_simulation_state() const
const std::unordered_set< Gate * > & get_gates() const
bool generate_vcd(const std::filesystem::path &path, u32 start_time, u32 end_time, std::set< const Net * > nets={}) const
SimulationInput * get_simulation_input() const override
void set_input(const Net *net, BooleanFunction::Value value)
SimulationInput * mSimulationInput
uint64_t u64
Definition: defines.h:42
uint32_t u32
Definition: defines.h:41
Definition: defines.h:45
Net * net