36 #include <unordered_set>
40 class SimulationInput;
167 bool generate_vcd(
const std::filesystem::path& path,
u32 start_time,
u32 end_time, std::set<const Net*> nets = {})
const;
177 bool inputEvent(
const SimulationInputNetEvent& netEv)
override;
185 struct SimulationGate
188 std::vector<GatePin*> m_input_pins;
189 std::vector<const Net*> m_input_nets;
190 std::unordered_map<std::string, BooleanFunction::Value> m_input_values;
192 SimulationGate(
const Gate* gate);
193 virtual ~SimulationGate() =
default;
201 struct SimulationGateCombinational :
public SimulationGate
203 std::vector<GatePin*> m_output_pins;
204 std::vector<const Net*> m_output_nets;
205 std::unordered_map<const Net*, BooleanFunction> m_functions;
207 SimulationGateCombinational(
const Gate* gate);
215 struct SimulationGateSequential :
public SimulationGate
217 SimulationGateSequential(
const Gate* gate);
220 virtual bool simulate(
const Simulation& simulation,
const WaveEvent& event, std::map<std::pair<const Net*, u64>,
BooleanFunction::Value>& new_events) = 0;
221 virtual void clock(
const u64 current_time, std::map<std::pair<const Net*, u64>,
BooleanFunction::Value>& new_events) = 0;
227 struct SimulationGateFF :
public SimulationGateSequential
229 BooleanFunction m_clock_func;
230 BooleanFunction m_clear_func;
231 BooleanFunction m_preset_func;
232 BooleanFunction m_next_state_func;
233 std::vector<const Net*> m_state_output_nets;
234 std::vector<const Net*> m_state_inverted_output_nets;
235 std::vector<const Net*> m_clock_nets;
241 SimulationGateFF(
const Gate* gate);
244 bool simulate(
const Simulation& simulation,
const WaveEvent& event, std::map<std::pair<const Net*, u64>,
BooleanFunction::Value>& new_events)
override;
251 struct SimulationGateRAM :
public SimulationGateSequential
267 std::vector<Port> m_ports;
268 std::vector<u64> m_data;
270 std::vector<size_t> m_clocked_read_ports;
271 std::vector<size_t> m_clocked_write_ports;
273 SimulationGateRAM(
const Gate* gate);
280 bool m_is_initialized =
false;
283 u64 m_current_time = 0;
284 std::vector<WaveEvent> m_event_queue;
286 u64 m_timeout_iterations = 10000000ul;
287 u64 m_id_counter = 0;
289 std::unordered_map<const Net*, std::vector<std::pair<SimulationGate*, std::vector<const GatePin*>>>> m_successors;
290 std::vector<std::unique_ptr<SimulationGate>> m_sim_gates;
291 std::vector<SimulationGate*> m_sim_gates_raw;
294 void compute_input_nets();
295 void compute_output_nets();
296 void prepare_clock_events(
u64 nanoseconds);
297 void process_events(
u64 timeout);
Value
represents the type of the node
NetlistSimulatorFactory()
SimulationEngine * createEngine() const override
u64 get_simulation_timeout() const
void load_initial_values_from_netlist()
bool inputEvent(const SimulationInputNetEvent &netEv) override
std::vector< WaveEvent > get_simulation_events(u32 netId) const override
void set_iteration_timeout(u64 iterations)
void simulate(u64 picoseconds)
void initialize_sequential_gates(const std::function< bool(const Gate *)> &filter=nullptr)
void set_simulation_state(const Simulation &state)
void load_initial_values(BooleanFunction::Value value)
const Simulation & get_simulation_state() const
const std::unordered_set< Gate * > & get_gates() const
bool generate_vcd(const std::filesystem::path &path, u32 start_time, u32 end_time, std::set< const Net * > nets={}) const
SimulationInput * get_simulation_input() const override
void set_input(const Net *net, BooleanFunction::Value value)
SimulationInput * mSimulationInput
BooleanFunction enable_func
std::vector< GatePin * > address_pins
std::vector< GatePin * > data_pins
BooleanFunction clock_func