preprocessing.cpp File Reference

#include "hal_core/netlist/gate.h"
#include "hal_core/netlist/gate_library/gate_type_component/lut_component.h"
#include "hal_core/netlist/module.h"
#include "hal_core/netlist/net.h"
#include "hal_core/netlist/netlist.h"
#include "xilinx_toolbox/plugin_xilinx_toolbox.h"
#include <functional>

Include dependency graph for preprocessing.cpp:

Go to the source code of this file.

Namespaces
	hal
	hal::xilinx_toolbox

Functions
Result< std::monostate >	hal::xilinx_toolbox::split_lut (Gate *g, bool create_module=false)
	Split a single LUT6_2 gate into up to two separate LUT gates. More...
Result< u32 >	hal::xilinx_toolbox::split_luts (const std::vector< Gate * > &gates, bool create_module=false)
	Split a set of LUT6_2 gates into separate LUT gates. More...
Result< u32 >	hal::xilinx_toolbox::split_luts (Netlist *nl, const std::vector< Gate * > &gates={}, bool create_module=false)
	Split the LUT6_2 gates of the netlist, or of the given gates, into separate LUT gates. More...
Result< std::monostate >	hal::xilinx_toolbox::split_shift_register (Gate *g, bool create_module=false)
	Split a single shift register primitive into an equivalent chain of FDCE flip-flops. More...
Result< u32 >	hal::xilinx_toolbox::split_shift_registers (const std::vector< Gate * > &gates, bool create_module=false)
	Split a set of shift register primitives into equivalent FDCE flip-flop chains. More...
Result< u32 >	hal::xilinx_toolbox::split_shift_registers (Netlist *nl, const std::vector< Gate * > &gates={}, bool create_module=false)
	Split the shift register primitives of the netlist, or of the given gates, into FDCE flip-flop chains. More...
Result< u32 >	hal::xilinx_toolbox::remove_no_load_wires (Netlist *nl, const std::vector< Net * > &nets={})
	Remove the "no load wire" nets that Vivado writes for unused output pins. More...