hal::xilinx_toolbox Namespace Reference

Classes
struct	LOC
	Information on a LOC. More...
struct	CellData
	Data of a cell on the FPGA fabric. More...
class	GuiLayoutLocker
	Suppresses layout updates of the GUI for as long as the object exists. More...

Enumerations
enum	BELType {   A6LUT , B6LUT , C6LUT , D6LUT ,   A5LUT , B5LUT , C5LUT , D5LUT ,   F7AMUX , F7BMUX , F8MUX , CARRY4 ,   AFF , BFF , CFF , DFF ,   A5FF , B5FF , C5FF , D5FF ,   BUFG , INBUF_EN , OUTBUF }
	BEL types relevant for XDC file parsing. More...
enum	LOCType { SLICE , RAMB36 , BUFGCTRL , PIN }
	LOC types relevant for XDC file parsing. More...

Functions
Result< u32 >	split_luts (Netlist *nl, const std::vector< Gate * > &gates={})
	Split LUTs with two outputs into two separate LUT gates. More...
Result< u32 >	split_shift_registers (Netlist *nl, const std::vector< Gate * > &gates={})
	Split shift register primitives and replaces them with equivalent flip-flops chains. More...
Result< u32 >	remove_no_load_wires (Netlist *nl, const std::vector< Net * > &nets={})
	Remove the "no load wire" nets that Vivado writes for unused output pins. More...
Result< std::monostate >	parse_xdc_file (Netlist *nl, const std::filesystem::path &xdc_file)
	Parse an .xdc file and extract the position LOC and BEL data of each gate. More...

Detailed Description

Applies Xilinx-specific placement information from an XDC file to a netlist.

Enumeration Type Documentation

BELType

enum hal::xilinx_toolbox::BELType

BEL types relevant for XDC file parsing.

Enumerator
A6LUT	The 6-input LUT at position A of a slice.
B6LUT	The 6-input LUT at position B of a slice.
C6LUT	The 6-input LUT at position C of a slice.
D6LUT	The 6-input LUT at position D of a slice.
A5LUT	The 5-input LUT at position A of a slice.
B5LUT	The 5-input LUT at position B of a slice.
C5LUT	The 5-input LUT at position C of a slice.
D5LUT	The 5-input LUT at position D of a slice.
F7AMUX	The F7 multiplexer that combines the LUTs at positions A and B.
F7BMUX	The F7 multiplexer that combines the LUTs at positions C and D.
F8MUX	The F8 multiplexer that combines the outputs of both F7 multiplexers.
CARRY4	The 4-bit carry chain of a slice.
AFF	The main flip-flop at position A of a slice.
BFF	The main flip-flop at position B of a slice.
CFF	The main flip-flop at position C of a slice.
DFF	The main flip-flop at position D of a slice.
A5FF	The secondary flip-flop at position A of a slice.
B5FF	The secondary flip-flop at position B of a slice.
C5FF	The secondary flip-flop at position C of a slice.
D5FF	The secondary flip-flop at position D of a slice.
BUFG	A global clock buffer.
INBUF_EN	The input buffer of an I/O block.
OUTBUF	The output buffer of an I/O block.

Definition at line 19 of file types.h.

LOCType

enum hal::xilinx_toolbox::LOCType

LOC types relevant for XDC file parsing.

Enumerator
SLICE	A logic slice of the FPGA fabric.
RAMB36	A 36 Kb block RAM of the FPGA fabric.
BUFGCTRL	A global clock buffer site of the FPGA fabric.
PIN	A package pin of the device.

Definition at line 54 of file types.h.

Function Documentation

parse_xdc_file()

Result< std::monostate > hal::xilinx_toolbox::parse_xdc_file	(	Netlist *	nl,
		const std::filesystem::path &	xdc_file
	)

Parse an .xdc file and extract the position LOC and BEL data of each gate.

Translates the coordinates extracted from the .xdc file into integer values.

Parameters

[in]	nl	- The netlist to operate on.
[in]	xdc_file	- The path to the .xdc file.

Returns

Ok() on success, an error otherwise.

Definition at line 220 of file xdc_parser.cpp.

References ERR.

Referenced by hal::PYBIND11_PLUGIN().

remove_no_load_wires()

Result< u32 > hal::xilinx_toolbox::remove_no_load_wires	(	Netlist *	nl,
		const std::vector< Net * > &	nets = {}
	)

Remove the "no load wire" nets that Vivado writes for unused output pins.

Vivado names such nets NLW_<instance>_<pin>_UNCONNECTED and only connects them to the output pin they stand in for. A net is removed if its name starts with NLW_ (or has NLW_ right after a / in a flattened path) and ends with _UNCONNECTED, optionally followed by a bit index such as (2) or [2], it has no destinations, and it is not a global output. The output pins that drove the removed nets are left unconnected.

Parameters

[in]	nl	- The netlist to operate on.
[in]	nets	- The nets to consider. Defaults to an empty vector, in which case all nets of the netlist are considered.

Returns

The number of removed nets on success, an error otherwise.

Definition at line 331 of file preprocessing.cpp.

References hal::Netlist::delete_net(), ERR, hal::Netlist::get_id(), hal::Netlist::get_nets(), log_info, name, and OK.

Referenced by hal::GuiExtensionXilinxToolbox::execute_function(), and hal::PYBIND11_PLUGIN().

split_luts()

Result< u32 > hal::xilinx_toolbox::split_luts	(	Netlist *	nl,
		const std::vector< Gate * > &	gates = {}
	)

Split LUTs with two outputs into two separate LUT gates.

Replaces LUT6_2 with a LUT6 and a LUT5 gate if the respective outputs of the LUT6_2 are actually used, i.e., connected to other gates.

Parameters

[in]	nl	- The netlist to operate on.
[in]	gates	- The gates to consider. Defaults to an empty vector, in which case all gates of the netlist are considered.

Returns

The number of split LUT6_2 gates on success, an error otherwise.

Definition at line 39 of file preprocessing.cpp.

References hal::Netlist::create_gate(), hal::Netlist::delete_gate(), ERR, hal::Gate::get_fan_in_endpoints(), hal::Gate::get_fan_in_net(), hal::Gate::get_fan_out_net(), hal::Netlist::get_gate_library(), hal::GateLibrary::get_gate_type_by_name(), hal::Gate::get_id(), hal::Netlist::get_id(), hal::Gate::get_init_data(), hal::Gate::get_module(), hal::Gate::get_name(), hal::Gate::get_type(), hal::Module::is_top_module(), log_info, log_warning, OK, and hal::DataContainer::set_data().

Referenced by hal::GuiExtensionXilinxToolbox::execute_function(), and hal::PYBIND11_PLUGIN().

split_shift_registers()

Result< u32 > hal::xilinx_toolbox::split_shift_registers	(	Netlist *	nl,
		const std::vector< Gate * > &	gates = {}
	)

Split shift register primitives and replaces them with equivalent flip-flops chains.

Currently only implemented for gate types SRL16E and SRLC32E. The created flip-flops are assigned to the module of the shift register gate that they replace.

Parameters

[in]	nl	- The netlist to operate on.
[in]	gates	- The gates to consider. Defaults to an empty vector, in which case all gates of the netlist are considered.

Returns

The number of split shift registers on success, an error otherwise.

Definition at line 141 of file preprocessing.cpp.

References hal::Net::add_destination(), hal::Net::add_source(), hal::clock, hal::control, hal::Netlist::create_gate(), hal::Netlist::create_net(), hal::data, hal::Netlist::delete_gate(), hal::enable, ERR, hal::Netlist::get_gate_library(), hal::GateLibrary::get_gate_type_by_name(), hal::Gate::get_id(), hal::Netlist::get_id(), hal::Gate::get_name(), hal::GateType::get_name(), hal::Net::get_num_of_destinations(), hal::Gate::get_type(), hal::input, hal::Net::is_gnd_net(), hal::Net::is_vcc_net(), log_info, log_warning, and OK.

Referenced by hal::GuiExtensionXilinxToolbox::execute_function(), and hal::PYBIND11_PLUGIN().