hal::xilinx_toolbox Namespace Reference

Classes
struct	LOC
	Information on a LOC. More...
struct	CellData
	Data of a cell on the FPGA fabric. More...
class	GuiLayoutLocker
	Suppresses layout updates of the GUI for as long as the object exists. More...

Enumerations
enum	BELType {   A6LUT , B6LUT , C6LUT , D6LUT ,   A5LUT , B5LUT , C5LUT , D5LUT ,   F7AMUX , F7BMUX , F8MUX , CARRY4 ,   AFF , BFF , CFF , DFF ,   A5FF , B5FF , C5FF , D5FF ,   BUFG , INBUF_EN , OUTBUF }
	BEL types relevant for XDC file parsing. More...
enum	LOCType { SLICE , RAMB36 , BUFGCTRL , PIN }
	LOC types relevant for XDC file parsing. More...

Functions
Result< std::monostate >	split_lut (Gate *g, bool create_module=false)
	Split a single LUT6_2 gate into up to two separate LUT gates. More...
Result< u32 >	split_luts (const std::vector< Gate * > &gates, bool create_module=false)
	Split a set of LUT6_2 gates into separate LUT gates. More...
Result< u32 >	split_luts (Netlist *nl, const std::vector< Gate * > &gates={}, bool create_module=false)
	Split the LUT6_2 gates of the netlist, or of the given gates, into separate LUT gates. More...
Result< std::monostate >	split_shift_register (Gate *g, bool create_module=false)
	Split a single shift register primitive into an equivalent chain of FDCE flip-flops. More...
Result< u32 >	split_shift_registers (const std::vector< Gate * > &gates, bool create_module=false)
	Split a set of shift register primitives into equivalent FDCE flip-flop chains. More...
Result< u32 >	split_shift_registers (Netlist *nl, const std::vector< Gate * > &gates={}, bool create_module=false)
	Split the shift register primitives of the netlist, or of the given gates, into FDCE flip-flop chains. More...
Result< u32 >	remove_no_load_wires (Netlist *nl, const std::vector< Net * > &nets={})
	Remove the "no load wire" nets that Vivado writes for unused output pins. More...
Result< std::monostate >	parse_xdc_file (Netlist *nl, const std::filesystem::path &xdc_file)
	Parse an .xdc file and extract the position LOC and BEL data of each gate. More...

Detailed Description

Applies Xilinx-specific placement information from an XDC file to a netlist.

Enumeration Type Documentation

BELType

enum hal::xilinx_toolbox::BELType

BEL types relevant for XDC file parsing.

Enumerator
A6LUT	The 6-input LUT at position A of a slice.
B6LUT	The 6-input LUT at position B of a slice.
C6LUT	The 6-input LUT at position C of a slice.
D6LUT	The 6-input LUT at position D of a slice.
A5LUT	The 5-input LUT at position A of a slice.
B5LUT	The 5-input LUT at position B of a slice.
C5LUT	The 5-input LUT at position C of a slice.
D5LUT	The 5-input LUT at position D of a slice.
F7AMUX	The F7 multiplexer that combines the LUTs at positions A and B.
F7BMUX	The F7 multiplexer that combines the LUTs at positions C and D.
F8MUX	The F8 multiplexer that combines the outputs of both F7 multiplexers.
CARRY4	The 4-bit carry chain of a slice.
AFF	The main flip-flop at position A of a slice.
BFF	The main flip-flop at position B of a slice.
CFF	The main flip-flop at position C of a slice.
DFF	The main flip-flop at position D of a slice.
A5FF	The secondary flip-flop at position A of a slice.
B5FF	The secondary flip-flop at position B of a slice.
C5FF	The secondary flip-flop at position C of a slice.
D5FF	The secondary flip-flop at position D of a slice.
BUFG	A global clock buffer.
INBUF_EN	The input buffer of an I/O block.
OUTBUF	The output buffer of an I/O block.

Definition at line 19 of file types.h.

LOCType

enum hal::xilinx_toolbox::LOCType

LOC types relevant for XDC file parsing.

Enumerator
SLICE	A logic slice of the FPGA fabric.
RAMB36	A 36 Kb block RAM of the FPGA fabric.
BUFGCTRL	A global clock buffer site of the FPGA fabric.
PIN	A package pin of the device.

Definition at line 54 of file types.h.

Function Documentation

parse_xdc_file()

Result< std::monostate > hal::xilinx_toolbox::parse_xdc_file	(	Netlist *	nl,
		const std::filesystem::path &	xdc_file
	)

Parse an .xdc file and extract the position LOC and BEL data of each gate.

Translates the coordinates extracted from the .xdc file into integer values.

Parameters

[in]	nl	- The netlist to operate on.
[in]	xdc_file	- The path to the .xdc file.

Returns

Ok() on success, an error otherwise.

Definition at line 220 of file xdc_parser.cpp.

References ERR.

Referenced by hal::PYBIND11_PLUGIN().

remove_no_load_wires()

Result< u32 > hal::xilinx_toolbox::remove_no_load_wires	(	Netlist *	nl,
		const std::vector< Net * > &	nets = {}
	)

Remove the "no load wire" nets that Vivado writes for unused output pins.

Vivado names such nets NLW_<instance>_<pin>_UNCONNECTED and only connects them to the output pin they stand in for. A net is removed if its name starts with NLW_ (or has NLW_ right after a / in a flattened path) and ends with _UNCONNECTED, optionally followed by a bit index such as (2) or [2], it has no destinations, and it is not a global output. The output pins that drove the removed nets are left unconnected.

Parameters

[in]	nl	- The netlist to operate on.
[in]	nets	- The nets to consider. Defaults to an empty vector, in which case all nets of the netlist are considered.

Returns

The number of removed nets on success, an error otherwise.

Definition at line 466 of file preprocessing.cpp.

References hal::Netlist::delete_net(), ERR, hal::Netlist::get_id(), hal::Netlist::get_nets(), log_info, name, and OK.

Referenced by hal::GuiExtensionXilinxToolbox::execute_function(), and hal::PYBIND11_PLUGIN().

split_lut()

Result< std::monostate > hal::xilinx_toolbox::split_lut	(	Gate *	g,
		bool	create_module = false
	)

Split a single LUT6_2 gate into up to two separate LUT gates.

Creates replacement gates depending on which outputs are connected:

• O6 → LUT6 using all 64 bits of the INIT string and all 6 inputs.
• O5 → LUT5 using bits [0, 31] of the INIT string and inputs I0-I4 (I5 is excluded, as it only selects the INIT half).

The original LUT6_2 gate is always deleted. The original INIT string is stored on each replacement gate under xilinx_preprocessing_information/original_init.

Parameters

[in]	g	- The LUT6_2 gate to split.
[in]	create_module	- If true, a new module named after the original gate is created as a child of its parent module and all replacement gates are placed into it. If false (default), replacement gates inherit the parent module of the original gate.

Returns

An empty OK result on success, an error if g is not of type LUT6_2, if the INIT string is malformed, or if the gate cannot be deleted.

Definition at line 78 of file preprocessing.cpp.

References hal::Module::assign_gate(), hal::Netlist::create_gate(), hal::Netlist::create_module(), hal::Netlist::delete_gate(), ERR, hal::GateTypeComponent::get_component_as(), hal::GateType::get_component_as(), hal::Gate::get_fan_in_endpoints(), hal::Gate::get_fan_out_net(), hal::Netlist::get_gate_library(), hal::GateLibrary::get_gate_type_by_name(), hal::Gate::get_id(), hal::LUTComponent::get_init_string(), hal::Gate::get_module(), hal::Gate::get_name(), hal::GateType::get_name(), hal::Gate::get_netlist(), hal::Gate::get_type(), hal::GateTypeComponent::get_type(), hal::Module::is_top_module(), log_warning, hal::GateTypeComponent::lut, OK, and hal::DataContainer::set_data().

Referenced by hal::PYBIND11_PLUGIN(), and split_luts().

split_luts() [1/2]

Result< u32 > hal::xilinx_toolbox::split_luts	(	const std::vector< Gate * > &	gates,
		bool	create_module = false
	)

Split a set of LUT6_2 gates into separate LUT gates.

Calls split_lut for each gate in gates. Gates that cannot be split are skipped with a warning; processing always continues with the remaining gates.

Parameters

[in]	gates	- The LUT6_2 gates to split.
[in]	create_module	- If true, each split gate's replacements are placed into a new module named after the original gate. If false (default), replacements inherit the parent module of the original gate.

Returns

The number of successfully split gates.

Definition at line 199 of file preprocessing.cpp.

References log_info, log_warning, OK, and split_lut().

Referenced by hal::GuiExtensionXilinxToolbox::execute_function(), hal::PYBIND11_PLUGIN(), and split_luts().

split_luts() [2/2]

Result< u32 > hal::xilinx_toolbox::split_luts	(	Netlist *	nl,
		const std::vector< Gate * > &	gates = {},
		bool	create_module = false
	)

Split the LUT6_2 gates of the netlist, or of the given gates, into separate LUT gates.

Finds all gates of type LUT6_2 within gates (or within the netlist if gates is empty) and calls split_luts(gates).

Parameters

[in]	nl	- The netlist to operate on.
[in]	gates	- The gates to consider. Defaults to an empty vector, in which case all gates of the netlist are considered.
[in]	create_module	- If true, each split gate's replacements are placed into a new module named after the original gate. If false (default), replacements inherit the parent module of the original gate.

Returns

The number of successfully split LUT6_2 gates.

Definition at line 217 of file preprocessing.cpp.

References hal::Gate::get_type(), and split_luts().

split_shift_register()

Result< std::monostate > hal::xilinx_toolbox::split_shift_register	(	Gate *	g,
		bool	create_module = false
	)

Split a single shift register primitive into an equivalent chain of FDCE flip-flops.

Supported gate types: SRL16, SRL16E, SRLC16E, SRLC32E.

Every address pin must be connected and driven by a constant (GND/VCC) net; an error is returned otherwise. The number of flip-flops created equals select_value + 1, where select_value is the binary value encoded by the address pins (A0 = bit 0). When the cascade output (Q15 for SRLC16E, Q31 for SRLC32E) has downstream consumers, all stages up to the maximum depth (15 or 31) are materialised so that the last flip-flop correctly drives the cascade net.

The original gate is always deleted on success.

Parameters

[in]	g	- The shift register gate to split.
[in]	create_module	- If true, a new module named after the original gate is created as a child of its parent module and all replacement flip-flops are placed into it. If false (default), replacement flip-flops inherit the parent module of the original gate.

Returns

An empty OK result on success, an error if g is not a supported shift register type, if any address pin is unconnected or not driven by a constant (GND/VCC) net, or if the gate cannot be deleted.

Definition at line 222 of file preprocessing.cpp.

References hal::Net::add_destination(), hal::Net::add_source(), hal::Module::assign_gate(), hal::clock, hal::control, hal::Netlist::create_gate(), hal::Netlist::create_module(), hal::Netlist::create_net(), hal::data, hal::Netlist::delete_gate(), hal::enable, ERR, hal::ff, hal::Net::get_destinations(), hal::BasePin< T >::get_direction(), hal::Gate::get_fan_in_net(), hal::Gate::get_fan_out_net(), hal::Netlist::get_gate_library(), hal::GateLibrary::get_gate_type_by_name(), hal::Gate::get_id(), hal::Gate::get_module(), hal::Gate::get_name(), hal::GateType::get_name(), hal::Gate::get_netlist(), hal::Net::get_num_of_destinations(), hal::DataContainer::get_parameter_value(), hal::GateType::get_pins(), hal::Gate::get_type(), hal::BasePin< T >::get_type(), hal::DataContainer::has_parameter(), hal::input, hal::Net::is_gnd_net(), hal::Module::is_top_module(), hal::Net::is_vcc_net(), log_warning, OK, and hal::Net::remove_destination().

Referenced by hal::PYBIND11_PLUGIN(), and split_shift_registers().

split_shift_registers() [1/2]

Result< u32 > hal::xilinx_toolbox::split_shift_registers	(	const std::vector< Gate * > &	gates,
		bool	create_module = false
	)

Split a set of shift register primitives into equivalent FDCE flip-flop chains.

Supported gate types: SRL16, SRL16E, SRLC16E, SRLC32E.

Calls split_shift_register for each gate in gates. Gates that cannot be split (e.g. because an address pin is not driven by a constant net) are skipped with a warning; processing always continues with the remaining gates.

Parameters

[in]	gates	- The shift register gates to split.
[in]	create_module	- If true, each split gate's replacements are placed into a new module named after the original gate. If false (default), replacements inherit the parent module of the original gate.

Returns

The number of successfully split gates.

Definition at line 443 of file preprocessing.cpp.

References log_info, log_warning, OK, and split_shift_register().

Referenced by hal::GuiExtensionXilinxToolbox::execute_function(), hal::PYBIND11_PLUGIN(), and split_shift_registers().

split_shift_registers() [2/2]

Result< u32 > hal::xilinx_toolbox::split_shift_registers	(	Netlist *	nl,
		const std::vector< Gate * > &	gates = {},
		bool	create_module = false
	)

Split the shift register primitives of the netlist, or of the given gates, into FDCE flip-flop chains.

Supported gate types: SRL16, SRL16E, SRLC16E, SRLC32E.

Finds all gates of one of the supported types within gates (or within the netlist if gates is empty) and calls split_shift_registers(gates).

Parameters

[in]	nl	- The netlist to operate on.
[in]	gates	- The gates to consider. Defaults to an empty vector, in which case all gates of the netlist are considered.
[in]	create_module	- If true, each split gate's replacements are placed into a new module named after the original gate. If false (default), replacements inherit the parent module of the original gate.

Returns

The number of successfully split shift register gates.

Definition at line 461 of file preprocessing.cpp.

References hal::GateType::get_name(), hal::Gate::get_type(), and split_shift_registers().