HAL  v4.5.0-133-g64838ea8d
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
preprocessing.h
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1 // MIT License
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3 // Copyright (c) 2019 Ruhr University Bochum, Chair for Embedded Security. All Rights reserved.
4 // Copyright (c) 2019 Marc Fyrbiak, Sebastian Wallat, Max Hoffmann ("ORIGINAL AUTHORS"). All rights reserved.
5 // Copyright (c) 2021 Max Planck Institute for Security and Privacy. All Rights reserved.
6 // Copyright (c) 2021 Jörn Langheinrich, Julian Speith, Nils Albartus, René Walendy, Simon Klix ("ORIGINAL AUTHORS"). All Rights reserved.
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25 
31 #pragma once
32 
33 #include "hal_core/defines.h"
35 
36 #include <vector>
37 
38 namespace hal
39 {
40  class Gate;
41  class Net;
42  class Netlist;
43 
44  namespace xilinx_toolbox
45  {
55  Result<u32> split_luts(Netlist* nl, const std::vector<Gate*>& gates = {});
56 
67  Result<u32> split_shift_registers(Netlist* nl, const std::vector<Gate*>& gates = {});
68 
80  Result<u32> remove_no_load_wires(Netlist* nl, const std::vector<Net*>& nets = {});
81 
91  Result<std::monostate> parse_xdc_file(Netlist* nl, const std::filesystem::path& xdc_file);
92  } // namespace xilinx_toolbox
93 } // namespace hal
Result< u32 > remove_no_load_wires(Netlist *nl, const std::vector< Net * > &nets={})
Remove the "no load wire" nets that Vivado writes for unused output pins.
Result< std::monostate > parse_xdc_file(Netlist *nl, const std::filesystem::path &xdc_file)
Parse an .xdc file and extract the position LOC and BEL data of each gate.
Definition: xdc_parser.cpp:220
Result< u32 > split_luts(Netlist *nl, const std::vector< Gate * > &gates={})
Split LUTs with two outputs into two separate LUT gates.
Result< u32 > split_shift_registers(Netlist *nl, const std::vector< Gate * > &gates={})
Split shift register primitives and replaces them with equivalent flip-flops chains.
Definition: defines.h:45