HAL  v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
preprocessing.h File Reference

This file contains functions specifically designed to preprocess Xilinx FPGA netlists. More...

Include dependency graph for preprocessing.h:

Go to the source code of this file.

Namespaces

 hal
 
 hal::xilinx_toolbox
 

Functions

Result< u32hal::xilinx_toolbox::split_luts (Netlist *nl)
 Split LUTs with two outputs into two separate LUT gates. More...
 
Result< u32hal::xilinx_toolbox::split_shift_registers (Netlist *nl)
 Split shift register primitives and replaces them with equivalent flip-flops chains. More...
 
Result< std::monostate > hal::xilinx_toolbox::parse_xdc_file (Netlist *nl, const std::filesystem::path &xdc_file)
 Parse an .xdc file and extract the position LOC and BEL data of each gate. More...
 

Detailed Description

This file contains functions specifically designed to preprocess Xilinx FPGA netlists.

Definition in file preprocessing.h.