|
HAL
v4.5.0-133-g64838ea8d
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
|
This file contains functions specifically designed to preprocess Xilinx FPGA netlists. More...

Go to the source code of this file.
Namespaces | |
| hal | |
| hal::xilinx_toolbox | |
Functions | |
| Result< u32 > | hal::xilinx_toolbox::split_luts (Netlist *nl, const std::vector< Gate * > &gates={}) |
| Split LUTs with two outputs into two separate LUT gates. More... | |
| Result< u32 > | hal::xilinx_toolbox::split_shift_registers (Netlist *nl, const std::vector< Gate * > &gates={}) |
| Split shift register primitives and replaces them with equivalent flip-flops chains. More... | |
| Result< u32 > | hal::xilinx_toolbox::remove_no_load_wires (Netlist *nl, const std::vector< Net * > &nets={}) |
| Remove the "no load wire" nets that Vivado writes for unused output pins. More... | |
| Result< std::monostate > | hal::xilinx_toolbox::parse_xdc_file (Netlist *nl, const std::filesystem::path &xdc_file) |
Parse an .xdc file and extract the position LOC and BEL data of each gate. More... | |
This file contains functions specifically designed to preprocess Xilinx FPGA netlists.
Definition in file preprocessing.h.