HAL  v4.5.0-254-g8f9f6a423
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
preprocessing.h File Reference

This file contains functions specifically designed to preprocess Xilinx FPGA netlists. More...

#include "hal_core/defines.h"
#include "hal_core/utilities/result.h"
#include <vector>
Include dependency graph for preprocessing.h:

Go to the source code of this file.

Namespaces

 hal
 
 hal::xilinx_toolbox
 

Functions

Result< std::monostate > hal::xilinx_toolbox::split_lut (Gate *g, bool create_module=false)
 Split a single LUT6_2 gate into up to two separate LUT gates. More...
 
Result< u32 > hal::xilinx_toolbox::split_luts (const std::vector< Gate * > &gates, bool create_module=false)
 Split a set of LUT6_2 gates into separate LUT gates. More...
 
Result< u32 > hal::xilinx_toolbox::split_luts (Netlist *nl, const std::vector< Gate * > &gates={}, bool create_module=false)
 Split the LUT6_2 gates of the netlist, or of the given gates, into separate LUT gates. More...
 
Result< std::monostate > hal::xilinx_toolbox::split_shift_register (Gate *g, bool create_module=false)
 Split a single shift register primitive into an equivalent chain of FDCE flip-flops. More...
 
Result< u32 > hal::xilinx_toolbox::split_shift_registers (const std::vector< Gate * > &gates, bool create_module=false)
 Split a set of shift register primitives into equivalent FDCE flip-flop chains. More...
 
Result< u32 > hal::xilinx_toolbox::split_shift_registers (Netlist *nl, const std::vector< Gate * > &gates={}, bool create_module=false)
 Split the shift register primitives of the netlist, or of the given gates, into FDCE flip-flop chains. More...
 
Result< u32 > hal::xilinx_toolbox::remove_no_load_wires (Netlist *nl, const std::vector< Net * > &nets={})
 Remove the "no load wire" nets that Vivado writes for unused output pins. More...
 
Result< std::monostate > hal::xilinx_toolbox::parse_xdc_file (Netlist *nl, const std::filesystem::path &xdc_file)
 Parse an .xdc file and extract the position LOC and BEL data of each gate. More...
 

Detailed Description

This file contains functions specifically designed to preprocess Xilinx FPGA netlists.

Definition in file preprocessing.h.