Xilinx Toolbox

A collection of functions specifically designed to operate on Xilinx FPGA netlists.

xilinx_toolbox.parse_xdc_file(nl: hal_py.Netlist, xdc_file: os.PathLike) → bool

Parse an .xdc file and extract the position LOC and BEL data of each gate. Translates the coordinates extracted from the .xdc file into integer values.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.
xdc_file (path) – The path to the .xdc file.

Returns

True on success, False otherwise.

Return type

bool

xilinx_toolbox.split_luts(nl: hal_py.Netlist, gates: List[hal_py.Gate] = []) → Optional[int]

Split LUTs with two outputs into two separate LUT gates. Replaces LUT6_2 with a LUT6 and a LUT5 gate if the respective outputs of the LUT6_2 are actually used, i.e., connected to other gates.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.
gates (list[hal_py.Gate]) – The gates to consider. Defaults to an empty list, in which case all gates of the netlist are considered.

Returns

The number of split LUT6_2 gates on success, None otherwise.

Return type

int or None

xilinx_toolbox.split_shift_registers(nl: hal_py.Netlist, gates: List[hal_py.Gate] = []) → Optional[int]

Split shift register primitives and replaces them with equivalent flip-flops chains. Currently only implemented for gate types SRL16E and SRLC32E. The created flip-flops are assigned to the module of the shift register gate that they replace.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.
gates (list[hal_py.Gate]) – The gates to consider. Defaults to an empty list, in which case all gates of the netlist are considered.

Returns