Netlist Preprocessing

hal NetlistPreprocessingPlugin python bindings

netlist_preprocessing.create_multi_bit_gate_modules(nl: hal_py.Netlist, concatenated_pin_groups: Dict[str, Dict[str, List[str]]]) → List[hal_py.Module]

Create modules from large gates like RAMs and DSPs with the option to concat multiple gate pin groups to larger consecutive pin groups.

Parameters

  • nl (hal_py.Netlist) – The netlist to operate on.

  • concatenated_pin_groups –

Returns

True on success, False otherwise.

Return type

bool

netlist_preprocessing.create_nets_at_unconnected_pins(nl: hal_py.Netlist) → List[hal_py.Net]
netlist_preprocessing.manual_mux_optimizations(nl: hal_py.Netlist, mux_inv_gl: hal_py.GateLibrary) → Optional[int]

Apply manually implemented optimizations to the netlist centered around muxes. Currently implemented optimizations include:

  • removing inverters incase there are inverter gates in front and behind every data input and output of the mux

  • optimizing and therefore unifying possible inverters preceding the select signals by resynthesizing

Parameters

  • nl (halp_py.Netlist) – The netlist to operate on.

  • mux_inv_gl (halp_py.GateLibrary) – A gate library only containing mux and inverter gates used for resynthesis.

Returns

The difference in the total number of gates caused by these optimizations.

Return type

int or None

netlist_preprocessing.parse_def_file(nl: hal_py.Netlist, def_file: os.PathLike) → bool

Parses a design exchange format file and extracts the coordinates of a placed design for each component/gate. The extracted coordinates get annotated to the gates.

Parameters
Returns

True on success, False otherwise.

Return type

bool

netlist_preprocessing.propagate_constants(nl: hal_py.Netlist) → Optional[int]

Builds for all gate output nets the Boolean function and substitutes all variables connected to vcc/gnd nets with the respective boolean value. If the function simplifies to a static boolean constant cut the connection to the nets destinations and directly connect it to vcc/gnd.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of rerouted nets on success, None otherwise.

Return type

int or None

netlist_preprocessing.reconstruct_indexed_ff_identifiers(nl: hal_py.Netlist) → Optional[int]

Tries to reconstruct a name and index for each flip flop that was part of a multi-bit wire in the verilog code. This is NOT a general netlist reverse engineering algorithm and ONLY works on synthesized netlists with names annotated by the synthesizer. This function mainly focuses netlists synthesized with yosys since yosys names the output wires of the flip flops but not the gate it self. We try to reconstruct name and index for each flip flop based on the name of its output nets.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of reconstructed names on success, None otherwise.

Return type

int or None

netlist_preprocessing.reconstruct_top_module_pin_groups(nl: hal_py.Netlist) → Optional[int]

Tries to reconstruct top module pin groups via indexed pin names.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of reconstructed pin groups on success, None otherwise.

Return type

int or None

netlist_preprocessing.remove_buffers(nl: hal_py.Netlist) → Optional[int]

Removes buffer gates from the netlist and connect their fan-in to their fan-out nets. Considers all combinational gates and takes their inputs into account. For example, a 2-input AND gate with one input being connected to constant 1 will also be removed.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of removed buffers on success, None otherwise.

Return type

int or None

netlist_preprocessing.remove_consecutive_inverters(nl: hal_py.Netlist) → Optional[int]

Removes two consecutive inverters and reconnects the input of the first inverter to the output of the second one. If the first inverter has additional successors, only the second inverter is deleted.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of removed inverter gates on success, None otherwise.

Return type

int or None

netlist_preprocessing.remove_redundant_gates(nl: hal_py.Netlist, filter: Callable[[hal_py.Gate], bool] = None) → Optional[int]

Removes redundant gates from the netlist, i.e., gates that are functionally equivalent and are connected to the same input nets.

Parameters

  • nl (hal_py.Netlist) – The netlist to operate on.

  • filter (lambda) – Optional filter to fine-tune which gates are being replaced. Default to a None.

Returns

The number of removed gates on success, None otherwise.

Return type

int or None

netlist_preprocessing.remove_redundant_logic_trees(nl: hal_py.Netlist) → Optional[int]

Removes redundant logic trees made up of combinational gates. If two trees compute the exact same function even if implemented with different gates we will disconnect one of the trees and afterwards clean up all dangling gates and nets.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of removed gates on success, None otherwise.

Return type

int or None

netlist_preprocessing.remove_redundant_loops(nl: hal_py.Netlist) → Optional[int]

Removes redundant sequential feedback loops. Sometimes flip-flops and some of their combinational fan-in form a feedback loop where the flip-flop input depends on its own output. For optimization, some synthesizers create multiple equivalent instances of these feedback loops. To simplify structural analysis, this function removes the redundant flip-flop gate of the loop from the netlist. Other preprocessing functions can then take care of the remaining combination gates of the loop.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of removed gates on success, None otherwise.

Return type

int or None

netlist_preprocessing.remove_unconnected_gates(nl: hal_py.Netlist) → Optional[int]

Removes gates for which all fan-out nets do not have a destination and are not global output nets.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of removed gates on success, None otherwise.

Return type

int or None

netlist_preprocessing.remove_unconnected_looped(nl: hal_py.Netlist) → Optional[int]

Calls remove_unconnected_gates / remove_unconnected_nets until there are no further changes.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of removed nets and gates on success, None otherwise.

Return type

int or None

netlist_preprocessing.remove_unconnected_nets(nl: hal_py.Netlist) → Optional[int]

Removes nets who have neither a source, nor a destination.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of removed nets on success, None otherwise.

Return type

int or None

netlist_preprocessing.remove_unused_lut_inputs(nl: hal_py.Netlist) → Optional[int]

Removes all LUT fan-in endpoints that do not correspond to a variable within the Boolean function that determines the output of a gate.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of removed LUT endpoints on success, None otherwise.

Return type

int or None

netlist_preprocessing.simplify_lut_inits(nl: hal_py.Netlist) → Optional[int]

Replaces pins connected to GND/VCC with constants and simplifies the boolean function of a LUT by recomputing the INIT string.

Parameters

nl (hal_py.Netlist) – The netlist to operate on.

Returns

The number of simplified INIT strings on success, None otherwise.

Return type

int or None

netlist_preprocessing.unify_ff_outputs(nl: hal_py.Netlist, ffs: List[hal_py.Gate] = [], inverter_type: hal_py.GateType = None) → Optional[int]

Iterates all flip-flops of the netlist or specified by the user. If a flip-flop has a state and a neg_state output, a new inverter gate is created and connected to the state output net as an additional destination. Finally, the neg_state output net is disconnected from the neg_state pin and re-connected to the new inverter gate’s output.

Parameters

  • nl (hal_py.Netlist) – The netlist to operate on.

  • ffs (list[hal_py.Gate]) – The flip-flops to operate on. Defaults to an empty vector, in which case all flip-flops of the netlist are considered.

  • inverter_type (hal_py.GateType) – The inverter gate type to use. Defaults to a None, in which case the first inverter type found in the gate library is used.

Returns

The number of rerouted neg_state outputs on success, None otherwise.

Return type

int or None

class netlist_preprocessing.NetlistPreprocessingPlugin
property dependencies

A set of plugin names that this plugin depends on.

Type

set[str]

property description

The description of the plugin.

Type

str

get_dependencies(self: netlist_preprocessing.NetlistPreprocessingPlugin) → Set[str]

Get a set of plugin names that this plugin depends on.

Returns

A set of plugin names that this plugin depends on.

Return type

set[str]

get_description(self: netlist_preprocessing.NetlistPreprocessingPlugin) → str

Get the description of the plugin.

Returns

The description of the plugin.

Return type

str

get_name(self: netlist_preprocessing.NetlistPreprocessingPlugin) → str

Get the name of the plugin.

Returns

Plugin name.

Return type

str

get_version(self: netlist_preprocessing.NetlistPreprocessingPlugin) → str

Get the version of the plugin.

Returns

Plugin version.

Return type

str

property name

The name of the plugin.

Type

str

property version

The version of the plugin.

Type

str