Resynthesis

Provides functions to decompose or re-synthesize combinational parts of a gate-level netlist.

resynthesis.decompose_gate(nl: hal_py.Netlist, gate: hal_py.Gate, delete_gate: bool = True) → bool

Decompose a combinational gate into a small circuit of AND, OR, XOR, and INVERT gates. For each output pin, the resolved Boolean function (only dependent on input pins) is determined. All these Boolean functions are then converted into a netlist using the previously mentioned primitive gates. The target gate is then replaced in the original netlist with the circuit that was just generated. The target gate is only deleted if delete_gate is set to True. Gate replacement will fail if the gate library of the netlist does not contain suitable AND, OR, XOR, and INVERT gate types.

Parameters

  • nl (hal_py.Netlist) – The netlist to operate on.

  • gate (hal_py.Gate) – The gate to decompose.

  • delete_gate (bool) – Set True to delete the original gate, False to keep it in the netlist. Defaults to True.

Returns

True on success, False otherwise.

Return type

bool

resynthesis.decompose_gates_of_type(nl: hal_py.Netlist, gate_types: List[hal_py.GateType]) → Optional[int]

Decompose all combinational gates of the specified types into small circuits of AND, OR, XOR, and INVERT gates. For all output pins of each gate, the resolved Boolean function (only dependent on input pins) is determined. All these Boolean functions are then converted into a circuit using the previously mentioned primitive gates. The target gates are then replaced (and thereby deleted) in the original netlist with the circuit that was just generated. Gate replacement will fail if the gate library of the netlist does not contain suitable AND, OR, XOR, and INVERT gate types.

Parameters
Returns

The number of decomposed gates on success, None otherwise.

Return type

int or None

resynthesis.resynthesize_gate(nl: hal_py.Netlist, gate: hal_py.Gate, target_gl: hal_py.GateLibrary, delete_gate: bool = True) → bool

Re-synthesize a combinational gate by calling Yosys on a functional description of the gate using a reduced gate library. For all output pins of each gate, the resolved Boolean function (only dependent on input pins) is determined. All these Boolean functions are then written to an HDL file that is functionally equivalent to the target gate. This file is fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. The provided gate library should be a subset of the gate library that was used to parse the netlist. The target gate is then replaced in the original netlist with the circuit that was just generated. The target gate is only deleted if delete_gate is set to True.

Parameters

  • nl (hal_py.Netlist) – The netlist to operate on.

  • gate (hal_py.Gate) – The gate to re-synthesize.

  • target_gl (hal_py.GateLibrary) – The gate library that is a subset of the gate library used to parse the netlist.

  • delete_gate (bool) – Set True to delete the original gate, False to keep it in the netlist. Defaults to True.

Returns

True on success, False otherwise.

Return type

bool

resynthesis.resynthesize_gates(nl: hal_py.Netlist, gates: List[hal_py.Gate], target_gl: hal_py.GateLibrary) → Optional[int]

Re-synthesize all specified combinational gates by calling Yosys on a functional description of the gates using a reduced gate library. For all output pins of each gate, the resolved Boolean function (only dependent on input pins) is determined. All Boolean functions of a gate are then written to an HDL file that is functionally equivalent to the gate. These files are fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. The provided gate library should be a subset of the gate library that was used to parse the netlist. The gates are then replaced in the original netlist with the circuits that were just generated. This process is repeated for every gate, hence they are re-synthesized in isolation.

Parameters

  • nl (hal_py.Netlist) – The netlist to operate on.

  • g (hal_py.Gate) – The gates to re-synthesize.

  • target_gl (hal_py.GateLibrary) – The gate library that is a subset of the gate library used to parse the netlist.

Returns

The number of re-synthesized gates on success, None otherwise.

Return type

int or None

resynthesis.resynthesize_gates_of_type(nl: hal_py.Netlist, gate_types: List[hal_py.GateType], target_gl: hal_py.GateLibrary) → Optional[int]

Re-synthesize all combinational gates of the specified types by calling Yosys on a functional description of the gates using a reduced gate library. For all output pins of each gate, the resolved Boolean function (only dependent on input pins) is determined. All Boolean functions of a gate are then written to an HDL file that is functionally equivalent to the gate. These files are fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. The provided gate library should be a subset of the gate library that was used to parse the netlist. The gates are then replaced in the original netlist with the circuits that were just generated. This process is repeated for every gate, hence they are re-synthesized in isolation.

Parameters
Returns

The number of re-synthesized gates on success, None otherwise.

Return type

int or None

resynthesis.resynthesize_subgraph(nl: hal_py.Netlist, subgraph: List[hal_py.Gate], target_gl: hal_py.GateLibrary) → Optional[int]

Re-synthesize the combinational gates of the subgraph by calling Yosys on a Verilog netlist representation of the subgraph using a reduced gate library. All gates of the subgraph are written to a Verilog netlist file which is then fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. The provided gate library should be a subset of the gate library that was used to parse the netlist. The gates are then replaced in the original netlist with the circuit that was just generated.

Parameters
Returns

The number of re-synthesized gates on success, None otherwise.

Return type

int or None

resynthesis.resynthesize_subgraph_of_type(nl: hal_py.Netlist, gate_types: List[hal_py.GateType], target_gl: hal_py.GateLibrary) → Optional[int]

Re-synthesize the combinational gates of the specified types as a subgraph by calling Yosys on a Verilog netlist representation of the subgraph induced by these gates using a reduced gate library. All gates of the subgraph are written to a Verilog netlist file which is then fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. The provided gate library should be a subset of the gate library that was used to parse the netlist. The gates are then replaced in the original netlist with the circuit that was just generated.

Parameters
Returns

The number of re-synthesized gates on success, None otherwise.

Return type

int or None

class resynthesis.ResynthesisPlugin

This class provides an interface to integrate the netlist resynthesis as a plugin within the HAL framework.

property dependencies

A set of plugin names that this plugin depends on.

Type

set[str]

property description

The description of the plugin.

Type

str

get_dependencies(self: resynthesis.ResynthesisPlugin) → Set[str]

Get a set of plugin names that this plugin depends on.

Returns

A set of plugin names that this plugin depends on.

Return type

set[str]

get_description(self: resynthesis.ResynthesisPlugin) → str

Get the description of the plugin.

Returns

The description of the plugin.

Return type

str

get_name(self: resynthesis.ResynthesisPlugin) → str

Get the name of the plugin.

Returns

The name of the plugin.

Return type

str

get_version(self: resynthesis.ResynthesisPlugin) → str

Get the version of the plugin.

Returns

The version of the plugin.

Return type

str

property name

The name of the plugin.

Type

str

property version

The version of the plugin.

Type

str