9 #include <unordered_set>
20 return std::make_unique<XilinxToolboxPlugin>();
25 return std::string(
"xilinx_toolbox");
30 return std::string(
"0.1");
35 return "A collection of functions specifically designed to operate on Xilinx FPGA netlists.";
49 std::vector<Gate*> gates_from_selection(
Netlist* nl,
const std::vector<u32>& mods,
const std::vector<u32>& gats)
51 std::vector<Gate*> res;
52 std::unordered_set<Gate*> seen;
54 const auto collect = [&res, &seen](
Gate* g) {
55 if (g !=
nullptr && seen.insert(g).second)
70 for (Gate* g : m->get_gates(
nullptr,
true))
83 std::vector<ContextMenuContribution> retval;
85 const auto add = [
this, &retval](
const std::string& tag,
const std::string& entry) {
90 retval.push_back(cmc);
94 if (!mods.empty() || !gats.empty())
96 add(
"split_luts_selection",
"Split LUTs of selection");
97 add(
"split_shift_registers_selection",
"Split shift registers of selection");
99 else if (!nets.empty())
101 add(
"remove_no_load_wires_selection",
"Remove no load wires of selection");
105 add(
"split_luts_netlist",
"Split LUTs of netlist");
106 add(
"split_shift_registers_netlist",
"Split shift registers of netlist");
107 add(
"remove_no_load_wires_netlist",
"Remove no load wires of netlist");
117 log_warning(
"xilinx_toolbox",
"cannot run preprocessing: no netlist loaded.");
126 std::vector<Gate*> scope;
127 if (tag ==
"split_luts_selection" || tag ==
"split_shift_registers_selection")
129 scope = gates_from_selection(nl, mods, gats);
132 log_warning(
"xilinx_toolbox",
"cannot run preprocessing on the selection: no gates selected.");
137 if (tag ==
"split_luts_selection" || tag ==
"split_luts_netlist")
141 log_error(
"xilinx_toolbox",
"failed to split LUTs: {}", res.get_error().get());
145 log_info(
"xilinx_toolbox",
"split {} LUTs.", res.get());
148 else if (tag ==
"split_shift_registers_selection" || tag ==
"split_shift_registers_netlist")
152 log_error(
"xilinx_toolbox",
"failed to split shift registers: {}", res.get_error().get());
156 log_info(
"xilinx_toolbox",
"split {} shift registers.", res.get());
159 else if (tag ==
"remove_no_load_wires_selection" || tag ==
"remove_no_load_wires_netlist")
161 std::vector<Net*> net_scope;
162 if (tag ==
"remove_no_load_wires_selection")
168 net_scope.push_back(n);
171 if (net_scope.empty())
173 log_warning(
"xilinx_toolbox",
"cannot remove no load wires of the selection: no nets selected.");
180 log_error(
"xilinx_toolbox",
"failed to remove no load wires: {}", res.get_error().get());
184 log_info(
"xilinx_toolbox",
"removed {} no load wires.", res.get());
189 log_warning(
"xilinx_toolbox",
"unknown context menu tag '{}'.", tag);
std::vector< AbstractExtensionInterface * > m_extensions
Gate * get_gate_by_id(const u32 gate_id) const
Module * get_module_by_id(u32 module_id) const
Net * get_net_by_id(u32 net_id) const
#define log_error(channel,...)
#define log_info(channel,...)
#define log_warning(channel,...)
std::unique_ptr< BasePluginInterface > create_plugin_instance()
This file contains functions specifically designed to preprocess Xilinx FPGA netlists.