3 #include "pybind11/operators.h"
4 #include "pybind11/pybind11.h"
5 #include "pybind11/stl.h"
6 #include "pybind11/stl_bind.h"
10 namespace py = pybind11;
18 #ifdef PYBIND11_MODULE
19 PYBIND11_MODULE(xilinx_toolbox, m)
21 m.doc() =
"A collection of functions specifically designed to operate on Xilinx FPGA netlists.";
25 py::module m(
"xilinx_toolbox",
"A collection of functions specifically designed to operate on Xilinx FPGA netlists.");
28 py::class_<XilinxToolboxPlugin, RawPtrWrapper<XilinxToolboxPlugin>,
BasePluginInterface> py_xilinx_toolbox_plugin(
29 m,
"XilinxToolboxPlugin", R
"(This class provides an interface to integrate the Xilinx toolbox as a plugin within the HAL framework.)");
32 The name of the plugin.
38 Get the name of the plugin.
40 :returns: The name of the plugin.
45 The version of the plugin.
51 Get the version of the plugin.
53 :returns: The version of the plugin.
58 The description of the plugin.
64 Get the description of the plugin.
66 :returns: The description of the plugin.
71 A set of plugin names that this plugin depends on.
77 Get a set of plugin names that this plugin depends on.
79 :returns: A set of plugin names that this plugin depends on.
85 [](
Netlist* nl) -> std::optional<u32> {
93 log_error(
"python_context",
"{}", res.get_error().get());
99 Split LUTs with two outputs into two separate LUT gates.
100 Replaces ``LUT6_2`` with a ``LUT6`` and a ``LUT5`` gate if the respective outputs of the ``LUT6_2`` are actually used, i.e., connected to other gates.
102 :param hal_py.Netlist nl: The netlist to operate on.
103 :returns: The number of split ``LUT6_2`` gates on success, ``None`` otherwise.
108 "split_shift_registers",
109 [](
Netlist* nl) -> std::optional<u32> {
117 log_error(
"python_context",
"{}", res.get_error().get());
123 Split shift register primitives and replaces them with equivalent flip-flops chains.
124 Currently only implemented for gate type ``SRL16E``.
126 :param hal_py.Netlist nl: The netlist to operate on.
127 :returns: The number of split shift registers on success, ``None`` otherwise.
133 [](
Netlist* nl,
const std::filesystem::path& xdc_file) ->
bool {
141 log_error(
"python_context",
"{}", res.get_error().get());
148 Parse an ``.xdc`` file and extract the position LOC and BEL data of each gate.
149 Translates the coordinates extracted from the ``.xdc`` file into integer values.
151 :param hal_py.Netlist nl: The netlist to operate on.
152 :param path xdc_file: The path to the ``.xdc`` file.
153 :returns: ``True`` on success, ``False`` otherwise.
157 #ifndef PYBIND11_MODULE
#define log_error(channel,...)
const Module * module(const Gate *g, const NodeBoxes &boxes)
This file contains functions specifically designed to preprocess Xilinx FPGA netlists.