HAL  v4.5.0-130-g83e8bfb3f
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
configuration.h
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3 // Copyright (c) 2019 Ruhr University Bochum, Chair for Embedded Security. All Rights reserved.
4 // Copyright (c) 2019 Marc Fyrbiak, Sebastian Wallat, Max Hoffmann ("ORIGINAL AUTHORS"). All rights reserved.
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6 // Copyright (c) 2021 Jörn Langheinrich, Julian Speith, Nils Albartus, René Walendy, Simon Klix ("ORIGINAL AUTHORS"). All Rights reserved.
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25 
31 #pragma once
32 
33 #include "hal_core/defines.h"
34 
35 #include <map>
36 #include <string>
37 #include <utility>
38 #include <vector>
39 
40 namespace hal
41 {
42  class Gate;
43  class Net;
44  class Netlist;
45 
46  namespace solve_fsm
47  {
59  {
66 
71 
78  std::vector<Gate*> state_register = {};
79 
85  std::vector<Gate*> transition_logic = {};
86 
93  std::vector<std::pair<std::string, std::vector<Net*>>> outputs = {};
94 
101  std::map<Gate*, bool> initial_state = {};
102 
108  u32 timeout = 600000;
109 
116  bool brute_force = false;
117 
124  Configuration& with_state_register(const std::vector<Gate*>& state_register);
125 
132  Configuration& with_transition_logic(const std::vector<Gate*>& transition_logic);
133 
140  Configuration& with_outputs(const std::vector<std::pair<std::string, std::vector<Net*>>>& outputs);
141 
148  Configuration& with_initial_state(const std::map<Gate*, bool>& initial_state);
149 
157 
164  Configuration& with_brute_force(const bool brute_force = true);
165  };
166  } // namespace solve_fsm
167 } // namespace hal
uint32_t u32
Definition: defines.h:41
Result< StateTransitionGraph > solve_fsm(const Configuration &config)
Recover the state transition graph of an FSM from the netlist that implements it.
Definition: solve_fsm.cpp:622
Definition: defines.h:45
The configuration of a run of the FSM solver.
Definition: configuration.h:59
Configuration & with_brute_force(const bool brute_force=true)
Set whether to enumerate all states instead of using an SMT solver.
Configuration & with_transition_logic(const std::vector< Gate * > &transition_logic)
Set the combinational gates that compute the next state of the FSM.
Configuration & with_timeout(const u32 timeout)
Set the timeout for the underlying SMT solver.
u32 timeout
The timeout for the underlying SMT solver in milliseconds. Defaults to 600000 ms.
std::vector< Gate * > state_register
The flip-flops that make up the state register of the FSM.
Definition: configuration.h:78
Configuration & with_outputs(const std::vector< std::pair< std::string, std::vector< Net * >>> &outputs)
Set the outputs of the FSM that the solver should evaluate in each state.
Configuration(Netlist *nl)
Construct a new FSM solver configuration for the given netlist.
Configuration & with_state_register(const std::vector< Gate * > &state_register)
Set the flip-flops that make up the state register of the FSM.
Netlist * netlist
The netlist that implements the FSM.
Definition: configuration.h:70
std::vector< std::pair< std::string, std::vector< Net * > > > outputs
The outputs of the FSM, each given as a name and the nets that make up that output.
Definition: configuration.h:93
Configuration & with_initial_state(const std::map< Gate *, bool > &initial_state)
Set the initial value of each flip-flop of the state register.
bool brute_force
Enumerate all states instead of using an SMT solver. Defaults to false.
std::map< Gate *, bool > initial_state
The initial value of each flip-flop of the state register.
std::vector< Gate * > transition_logic
The combinational gates that compute the next state of the FSM.
Definition: configuration.h:85