HAL  v4.5.0-130-g83e8bfb3f
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
configuration.cpp
Go to the documentation of this file.
1 // MIT License
2 //
3 // Copyright (c) 2019 Ruhr University Bochum, Chair for Embedded Security. All Rights reserved.
4 // Copyright (c) 2019 Marc Fyrbiak, Sebastian Wallat, Max Hoffmann ("ORIGINAL AUTHORS"). All rights reserved.
5 // Copyright (c) 2021 Max Planck Institute for Security and Privacy. All Rights reserved.
6 // Copyright (c) 2021 Jörn Langheinrich, Julian Speith, Nils Albartus, René Walendy, Simon Klix ("ORIGINAL AUTHORS"). All Rights reserved.
7 //
8 // Permission is hereby granted, free of charge, to any person obtaining a copy
9 // of this software and associated documentation files (the "Software"), to deal
10 // in the Software without restriction, including without limitation the rights
11 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 // copies of the Software, and to permit persons to whom the Software is
13 // furnished to do so, subject to the following conditions:
14 //
15 // The above copyright notice and this permission notice shall be included in all
16 // copies or substantial portions of the Software.
17 //
18 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 // SOFTWARE.
25 
27 
28 namespace hal
29 {
30  namespace solve_fsm
31  {
33  {
34  }
35 
36  Configuration& Configuration::with_state_register(const std::vector<Gate*>& state_register)
37  {
38  this->state_register = state_register;
39  return *this;
40  }
41 
42  Configuration& Configuration::with_transition_logic(const std::vector<Gate*>& transition_logic)
43  {
44  this->transition_logic = transition_logic;
45  return *this;
46  }
47 
48  Configuration& Configuration::with_outputs(const std::vector<std::pair<std::string, std::vector<Net*>>>& outputs)
49  {
50  this->outputs = outputs;
51  return *this;
52  }
53 
54  Configuration& Configuration::with_initial_state(const std::map<Gate*, bool>& initial_state)
55  {
56  this->initial_state = initial_state;
57  return *this;
58  }
59 
61  {
62  this->timeout = timeout;
63  return *this;
64  }
65 
67  {
68  this->brute_force = brute_force;
69  return *this;
70  }
71  } // namespace solve_fsm
72 } // namespace hal
uint32_t u32
Definition: defines.h:41
Result< StateTransitionGraph > solve_fsm(const Configuration &config)
Recover the state transition graph of an FSM from the netlist that implements it.
Definition: solve_fsm.cpp:622
Definition: defines.h:45
This file contains the struct that holds the configuration of a run of the FSM solver.
The configuration of a run of the FSM solver.
Definition: configuration.h:59
Configuration & with_brute_force(const bool brute_force=true)
Set whether to enumerate all states instead of using an SMT solver.
Configuration & with_transition_logic(const std::vector< Gate * > &transition_logic)
Set the combinational gates that compute the next state of the FSM.
Configuration & with_timeout(const u32 timeout)
Set the timeout for the underlying SMT solver.
u32 timeout
The timeout for the underlying SMT solver in milliseconds. Defaults to 600000 ms.
std::vector< Gate * > state_register
The flip-flops that make up the state register of the FSM.
Definition: configuration.h:78
Configuration & with_outputs(const std::vector< std::pair< std::string, std::vector< Net * >>> &outputs)
Set the outputs of the FSM that the solver should evaluate in each state.
Configuration(Netlist *nl)
Construct a new FSM solver configuration for the given netlist.
Configuration & with_state_register(const std::vector< Gate * > &state_register)
Set the flip-flops that make up the state register of the FSM.
std::vector< std::pair< std::string, std::vector< Net * > > > outputs
The outputs of the FSM, each given as a name and the nets that make up that output.
Definition: configuration.h:93
Configuration & with_initial_state(const std::map< Gate *, bool > &initial_state)
Set the initial value of each flip-flop of the state register.
bool brute_force
Enumerate all states instead of using an SMT solver. Defaults to false.
std::map< Gate *, bool > initial_state
The initial value of each flip-flop of the state register.
std::vector< Gate * > transition_logic
The combinational gates that compute the next state of the FSM.
Definition: configuration.h:85