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HAL
v4.5.0-130-g83e8bfb3f
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
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The configuration of a run of the FSM solver. More...
#include </home/runner/work/hal/hal/plugins/solve_fsm/include/solve_fsm/configuration.h>

Public Member Functions | |
| Configuration (Netlist *nl) | |
| Construct a new FSM solver configuration for the given netlist. More... | |
| Configuration & | with_state_register (const std::vector< Gate * > &state_register) |
| Set the flip-flops that make up the state register of the FSM. More... | |
| Configuration & | with_transition_logic (const std::vector< Gate * > &transition_logic) |
| Set the combinational gates that compute the next state of the FSM. More... | |
| Configuration & | with_outputs (const std::vector< std::pair< std::string, std::vector< Net * >>> &outputs) |
| Set the outputs of the FSM that the solver should evaluate in each state. More... | |
| Configuration & | with_initial_state (const std::map< Gate *, bool > &initial_state) |
| Set the initial value of each flip-flop of the state register. More... | |
| Configuration & | with_timeout (const u32 timeout) |
| Set the timeout for the underlying SMT solver. More... | |
| Configuration & | with_brute_force (const bool brute_force=true) |
| Set whether to enumerate all states instead of using an SMT solver. More... | |
Public Attributes | |
| Netlist * | netlist |
| The netlist that implements the FSM. More... | |
| std::vector< Gate * > | state_register = {} |
| The flip-flops that make up the state register of the FSM. More... | |
| std::vector< Gate * > | transition_logic = {} |
| The combinational gates that compute the next state of the FSM. More... | |
| std::vector< std::pair< std::string, std::vector< Net * > > > | outputs = {} |
| The outputs of the FSM, each given as a name and the nets that make up that output. More... | |
| std::map< Gate *, bool > | initial_state = {} |
| The initial value of each flip-flop of the state register. More... | |
| u32 | timeout = 600000 |
| The timeout for the underlying SMT solver in milliseconds. Defaults to 600000 ms. More... | |
| bool | brute_force = false |
Enumerate all states instead of using an SMT solver. Defaults to false. More... | |
The configuration of a run of the FSM solver.
Holds everything the solver needs to know about the FSM, including the netlist that implements it. The state register and the transition logic are mandatory, everything else is optional.
States are encoded as integers, with the first flip-flop of the state register providing the least significant bit.
Definition at line 58 of file configuration.h.
| hal::solve_fsm::Configuration::Configuration | ( | Netlist * | nl | ) |
Construct a new FSM solver configuration for the given netlist.
| [in] | nl | - The netlist that implements the FSM. |
Definition at line 32 of file configuration.cpp.
| Configuration & hal::solve_fsm::Configuration::with_brute_force | ( | const bool | brute_force = true | ) |
Set whether to enumerate all states instead of using an SMT solver.
| [in] | brute_force | - Set true to enumerate all states, false to use an SMT solver. Defaults to true. |
Definition at line 66 of file configuration.cpp.
References brute_force.
Referenced by hal::PYBIND11_PLUGIN().
| Configuration & hal::solve_fsm::Configuration::with_initial_state | ( | const std::map< Gate *, bool > & | initial_state | ) |
Set the initial value of each flip-flop of the state register.
| [in] | initial_state | - The initial value of each flip-flop of the state register. |
Definition at line 54 of file configuration.cpp.
References initial_state.
Referenced by hal::PYBIND11_PLUGIN().
| Configuration & hal::solve_fsm::Configuration::with_outputs | ( | const std::vector< std::pair< std::string, std::vector< Net * >>> & | outputs | ) |
Set the outputs of the FSM that the solver should evaluate in each state.
| [in] | outputs | - The outputs, each given as a name and the nets that make up that output, least significant bit first. |
Definition at line 48 of file configuration.cpp.
References outputs.
Referenced by hal::PYBIND11_PLUGIN().
| Configuration & hal::solve_fsm::Configuration::with_state_register | ( | const std::vector< Gate * > & | state_register | ) |
Set the flip-flops that make up the state register of the FSM.
| [in] | state_register | - The flip-flops of the state register, least significant bit first. |
Definition at line 36 of file configuration.cpp.
References state_register.
Referenced by hal::PYBIND11_PLUGIN().
| Configuration & hal::solve_fsm::Configuration::with_timeout | ( | const u32 | timeout | ) |
Set the timeout for the underlying SMT solver.
| [in] | timeout | - The timeout in milliseconds. |
Definition at line 60 of file configuration.cpp.
References timeout.
Referenced by hal::PYBIND11_PLUGIN().
| Configuration & hal::solve_fsm::Configuration::with_transition_logic | ( | const std::vector< Gate * > & | transition_logic | ) |
Set the combinational gates that compute the next state of the FSM.
| [in] | transition_logic | - The gates of the transition logic. |
Definition at line 42 of file configuration.cpp.
References transition_logic.
Referenced by hal::PYBIND11_PLUGIN().
| bool hal::solve_fsm::Configuration::brute_force = false |
Enumerate all states instead of using an SMT solver. Defaults to false.
Brute forcing needs no external solver and is faster for small state registers, but its runtime doubles with every additional flip-flop. Both approaches produce the same state transition graph.
Definition at line 116 of file configuration.h.
Referenced by hal::PYBIND11_PLUGIN(), hal::solve_fsm::solve_fsm(), and with_brute_force().
| std::map<Gate*, bool> hal::solve_fsm::Configuration::initial_state = {} |
The initial value of each flip-flop of the state register.
Only states reachable from the resulting initial state are explored. Defaults to an empty map, in which case the FSM starts in state 0.
Definition at line 101 of file configuration.h.
Referenced by hal::PYBIND11_PLUGIN(), hal::solve_fsm::solve_fsm(), and with_initial_state().
| Netlist* hal::solve_fsm::Configuration::netlist |
The netlist that implements the FSM.
Definition at line 70 of file configuration.h.
Referenced by hal::PYBIND11_PLUGIN(), and hal::solve_fsm::solve_fsm().
| std::vector<std::pair<std::string, std::vector<Net*> > > hal::solve_fsm::Configuration::outputs = {} |
The outputs of the FSM, each given as a name and the nets that make up that output.
The first net of an output provides its least significant bit, so a single-bit output is a vector holding one net. Defaults to an empty vector, in which case no outputs are computed.
Definition at line 93 of file configuration.h.
Referenced by hal::PYBIND11_PLUGIN(), hal::solve_fsm::solve_fsm(), and with_outputs().
| std::vector<Gate*> hal::solve_fsm::Configuration::state_register = {} |
The flip-flops that make up the state register of the FSM.
The first flip-flop provides the least significant bit of the state. Defaults to an empty vector, but a state register is required for the solver to run.
Definition at line 78 of file configuration.h.
Referenced by hal::PYBIND11_PLUGIN(), hal::solve_fsm::solve_fsm(), and with_state_register().
| u32 hal::solve_fsm::Configuration::timeout = 600000 |
The timeout for the underlying SMT solver in milliseconds. Defaults to 600000 ms.
Has no effect when brute_force is set, as no SMT solver is used then.
Definition at line 108 of file configuration.h.
Referenced by hal::PYBIND11_PLUGIN(), hal::solve_fsm::solve_fsm(), and with_timeout().
| std::vector<Gate*> hal::solve_fsm::Configuration::transition_logic = {} |
The combinational gates that compute the next state of the FSM.
Defaults to an empty vector, but transition logic is required for the solver to run.
Definition at line 85 of file configuration.h.
Referenced by hal::PYBIND11_PLUGIN(), hal::solve_fsm::solve_fsm(), and with_transition_logic().