#include </home/runner/work/hal/hal/plugins/simulator/verilator/include/verilator/verilator.h>

Inheritance diagram for hal::verilator::VerilatorEngine:

Collaboration diagram for hal::verilator::VerilatorEngine:

Public Member Functions
	VerilatorEngine (const std::string &nam)

bool	setSimulationInput (SimulationInput *simInput) override

int	numberCommandLines () const override

std::vector< std::string >	commandLine (int lineIndex) const override

bool	finalize () override

Public Member Functions inherited from hal::SimulationEngineScripted
	SimulationEngineScripted (const std::string &nam)

Public Member Functions inherited from hal::SimulationEngine
	SimulationEngine (const std::string &nam)

virtual	~SimulationEngine ()

std::string	name () const

State	state () const

int	get_state () const

std::string	get_working_directory () const

void	set_working_directory (const std::string &workDir)

bool	clock_events_required () const

bool	can_share_memory () const

bool	install_saleae_parser (std::string dirname) const

virtual void	setResultFilename (const std::string filename)

std::string	get_result_filename () const

virtual void	failed ()

virtual void	set_engine_property (const std::string &key, const std::string &value)

virtual std::string	get_engine_property (const std::string &key)

virtual const std::unordered_map< std::string, std::string > &	get_engine_properties () const

virtual SimulationInput *	get_simulation_input () const

Public Attributes
std::unique_ptr< Netlist >	m_partial_netlist

std::filesystem::path	m_simulator_dir

std::string	m_design_name

Additional Inherited Members
Public Types inherited from hal::SimulationEngine
enum	State { Failed = -1 , Done = 0 , Running = 1 , Preparing = 2 }

Protected Attributes inherited from hal::SimulationEngine
bool	mRequireClockEvents

bool	mCanShareMemory

std::string	mResultFilename

State	mState

std::unordered_map< std::string, std::string >	mProperties

SimulationInput *	mSimulationInput

std::string	mWorkDir

Detailed Description

A simulation engine that translates the netlist into Verilog and simulates it using Verilator.

Definition at line 161 of file verilator.h.

Constructor & Destructor Documentation

◆ VerilatorEngine()

hal::verilator::VerilatorEngine::VerilatorEngine ( const std::string & nam )

Definition at line 297 of file verilator.cpp.

References hal::SimulationEngine::mRequireClockEvents.

Member Function Documentation

◆ commandLine()

std::vector< std::string > hal::verilator::VerilatorEngine::commandLine ( int lineIndex ) const

overridevirtual

Must be implemented by derived class

Returns command and argument to be executed

Parameters

[in] lineIndex the line index of the script starting from 0

Returns: first element is command to be executed, subsequent elements are arguments

Implements hal::SimulationEngineScripted.

Definition at line 225 of file verilator.cpp.

References m_design_name, path_to_rapidjson_includedir, and path_to_verilator_executable.

◆ finalize()

bool hal::verilator::VerilatorEngine::finalize ( )

overridevirtual

Can be overwritten by derived class

Signals the engine that it is time for final steps (.e.g. writing VCD file) after simulation is done - that is: SimulationEngineEventDriven: all input events have been processed SimulationEngineScripted: all comands executed successfully