HAL  v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
converter.cpp File Reference
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Namespaces

 hal
 
 hal::verilator
 
 hal::verilator::converter
 

Functions

bool hal::verilator::converter::convert_gate_library_to_verilog (const Netlist *nl, const std::filesystem::path verilator_sim_path, const std::filesystem::path model_path="")
 
std::set< std::string > hal::verilator::converter::get_provided_models (const std::filesystem::path model_path, const std::filesystem::path gate_definition_path)
 
std::unordered_map< GateType *, std::string > hal::verilator::converter::get_gate_gate_types_from_netlist (const Netlist *nl)
 
std::string hal::verilator::converter::get_name_for_gate_type (const GateType *gt)
 
std::vector< std::string > hal::verilator::converter::get_parameters_for_gate (const GateType *gt)
 
std::string hal::verilator::converter::get_prologue_for_gate_type (const GateType *gt)
 
Result< std::string > hal::verilator::converter::verilog_function_printer (const BooleanFunction::Node &node, std::vector< std::string > &&operands)
 
std::string hal::verilator::converter::get_function_for_gate (const GateType *gt)
 
std::string hal::verilator::converter::get_epilogue_for_gate_type ()