verilator.h

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// MIT License
// 
// Copyright (c) 2019 Ruhr University Bochum, Chair for Embedded Security. All Rights reserved.
// Copyright (c) 2019 Marc Fyrbiak, Sebastian Wallat, Max Hoffmann ("ORIGINAL AUTHORS"). All rights reserved.
// Copyright (c) 2021 Max Planck Institute for Security and Privacy. All Rights reserved.
// Copyright (c) 2021 Jörn Langheinrich, Julian Speith, Nils Albartus, René Walendy, Simon Klix ("ORIGINAL AUTHORS"). All Rights reserved.
// 
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// 
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
// 
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
 
#pragma once
 
#include "hal_core/defines.h"
#include "netlist_simulator_controller/simulation_engine.h"
 
#include <filesystem>
#include <set>
#include <vector>
 
namespace hal
{
    class Netlist;
    class Gate;
    class GateType;
    class Net;
 
    namespace verilator
    {
        namespace converter
        {
            bool convert_gate_library_to_verilog(const Netlist* nl, const std::filesystem::path verilator_sim_path, const std::filesystem::path model_path = "");
 
            std::set<std::string> get_provided_models(const std::filesystem::path model_path, const std::filesystem::path gate_definition_path);
 
            std::unordered_map<GateType *, std::string> get_gate_gate_types_from_netlist(const Netlist* nl);
 
            std::vector<std::string> get_parameters_for_gate(const GateType* gt);
 
            std::string get_name_for_gate_type(const GateType* gt);
 
            std::string get_prologue_for_gate_type(const GateType* gt);
 
            Result<std::string> verilog_function_printer(const BooleanFunction::Node& node, std::vector<std::string>&& operands);
 
            // gate functionality
            std::string get_function_for_gate(const GateType* gt);
 
            std::string get_function_for_lut(const GateType* gt);
 
            std::string get_function_for_combinational_gate(const GateType* gt);
 
            std::string get_function_for_ff(const GateType* gt);
 
            std::string get_function_for_latch(const GateType* gt);
 
            std::string get_epilogue_for_gate_type();
        }    // namespace converter
 
        class VerilatorEngine : public SimulationEngineScripted
        {
            // path to VCD file with results when simulation done is SimulationEngine::mResultFilename
 
            static const int s_command_lines;
 
        public:
            VerilatorEngine(const std::string& nam);
            std::unique_ptr<Netlist> m_partial_netlist;
            std::filesystem::path m_simulator_dir;
 
            std::string m_design_name;
 
            bool setSimulationInput(SimulationInput* simInput) override;
            int numberCommandLines() const override;
            std::vector<std::string> commandLine(int lineIndex) const override;
            bool finalize() override;
 
        private:
            bool write_testbench_files(SimulationInput* simInput);
            int m_num_of_threads = 4;
            std::string m_compiler;
        };
 
        class VerilatorEngineFactory : public SimulationEngineFactory
        {
        public:
            VerilatorEngineFactory() : SimulationEngineFactory("verilator")
            {
            }
            SimulationEngine* createEngine() const override;
        };
    }    // namespace verilator
 
}    // namespace hal