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HAL
v4.5.0-83-g30c8f0afc
The Hardware Analyzer - a comprehensive reverse engineering and manipulation framework for gate-level netlists.
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#include "hal_core/defines.h"#include "netlist_simulator_controller/simulation_engine.h"#include <filesystem>#include <set>#include <vector>
Go to the source code of this file.
Classes | |
| class | hal::verilator::VerilatorEngine |
| class | hal::verilator::VerilatorEngineFactory |
Namespaces | |
| hal | |
| hal::verilator | |
| hal::verilator::converter | |
Functions | |
| bool | hal::verilator::converter::convert_gate_library_to_verilog (const Netlist *nl, const std::filesystem::path verilator_sim_path, const std::filesystem::path model_path="") |
| std::set< std::string > | hal::verilator::converter::get_provided_models (const std::filesystem::path model_path, const std::filesystem::path gate_definition_path) |
| std::unordered_map< GateType *, std::string > | hal::verilator::converter::get_gate_gate_types_from_netlist (const Netlist *nl) |
| std::vector< std::string > | hal::verilator::converter::get_parameters_for_gate (const GateType *gt) |
| std::string | hal::verilator::converter::get_name_for_gate_type (const GateType *gt) |
| std::string | hal::verilator::converter::get_prologue_for_gate_type (const GateType *gt) |
| Result< std::string > | hal::verilator::converter::verilog_function_printer (const BooleanFunction::Node &node, std::vector< std::string > &&operands) |
| std::string | hal::verilator::converter::get_function_for_gate (const GateType *gt) |
| std::string | hal::verilator::converter::get_function_for_lut (const GateType *gt) |
| std::string | hal::verilator::converter::get_function_for_combinational_gate (const GateType *gt) |
| std::string | hal::verilator::converter::get_function_for_ff (const GateType *gt) |
| std::string | hal::verilator::converter::get_function_for_latch (const GateType *gt) |
| std::string | hal::verilator::converter::get_epilogue_for_gate_type () |